公开(公告)号：US20170032755A1

公开(公告)日：2017-02-02

申请号：US15206500

申请日：2016-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju Hyun Ko ,  Yong Joo Song ,  Jun Ho Song

IPC: G09G3/36 ,  H03F3/45

Abstract: A buffer amplifier circuit includes a buffer amplifier including a first differential amplifier having a first active load and a second differential amplifier having a second active load and a feedback circuit configured to feed an output signal of an output terminal of the buffer amplifier back to one of the first and second active loads using differential switch signals and an input signal of the buffer amplifier to enhance a slew rate of the output signal.

Abstract translation: 缓冲放大器电路包括缓冲放大器，该缓冲放大器包括具有第一有源负载的第一差分放大器和具有第二有源负载的第二差分放大器和被配置为将缓冲放大器的输出端的输出信号反馈到 第一和第二有源负载使用差分开关信号和缓冲放大器的输入信号来增强输出信号的转换速率。

公开(公告)号：US11127366B2

公开(公告)日：2021-09-21

申请号：US16808824

申请日：2020-03-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ha Jun Lee ,  Jun Ho Song ,  Jeong Ah Ahn ,  Eun Jong Jang

IPC: G09G3/36 ,  G09G3/3258

Abstract: A source driver including a decoder configured to receive image data and an activation signal, determine a target voltage based on the image data, and select at least one gamma line for generating the target voltage from among a plurality of gamma lines, which are configured to transmit different gamma voltages, respectively, and a buffer circuit including a plurality of input terminals and configured to be connected to the selected at least one gamma line and generate an output voltage based on at least one gamma voltage obtained from the selected at least one gamma line may be provided. The decoder may be further configured to select a gamma line group including the selected at least one gamma line to be connected to the plurality of input terminals of the buffer circuit during a slew period of the buffer circuit in accordance with the activation signal.

公开(公告)号：US20210012743A1

公开(公告)日：2021-01-14

申请号：US16808824

申请日：2020-03-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ha Jun LEE ,  Jun Ho Song ,  Jeong Ah Ahn ,  Eun Jong Jang

IPC: G09G3/36 ,  G09G3/3258

Abstract: A source driver including a decoder configured to receive image data and an activation signal, determine a target voltage based on the image data, and select at least one gamma line for generating the target voltage from among a plurality of gamma lines, which are configured to transmit different gamma voltages, respectively, and a buffer circuit including a plurality of input terminals and configured to be connected to the selected at least one gamma line and generate an output voltage based on at least one gamma voltage obtained from the selected at least one gamma line may be provided. The decoder may be further configured to select a gamma line group including the selected at least one gamma line to be connected to the plurality of input terminals of the buffer circuit during a slew period of the buffer circuit in accordance with the activation signal.

公开(公告)号：US10467973B2

公开(公告)日：2019-11-05

申请号：US15206500

申请日：2016-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju Hyun Ko ,  Yong Joo Song ,  Jun Ho Song

IPC: G09G3/36 ,  H03F3/45 ,  H03F3/30

Abstract: A buffer amplifier circuit includes a buffer amplifier including a first differential amplifier having a first active load and a second differential amplifier having a second active load and a feedback circuit configured to feed an output signal of an output terminal of the buffer amplifier back to one of the first and second active loads using differential switch signals and an input signal of the buffer amplifier to enhance a slew rate of the output signal.

公开(公告)号：US09171514B2

公开(公告)日：2015-10-27

申请号：US14015166

申请日：2013-08-30

Applicant: Samsung Electronics Co., Ltd

Inventor： Yang Wook Kim ,  Suk Yun Woo ,  Jun Ho Song ,  Seong Jong Yoo ,  Dong Min Lee ,  Kyung Gyu Park ,  Hyung Woo Yu

IPC: G09G3/36

CPC classification number: G09G3/3674 ,  G09G3/3614 ,  G09G3/3688 ,  G09G2310/0294 ,  G09G2310/0297

Abstract: A method of muxing data by using clock signals having different timings and an apparatus performing the method are provided. Storing and muxing (or dividing) the data are simultaneously performed. The apparatus includes a first latch circuit arranging data blocks, which are input in series, in parallel in response to non-overlapping latch control signals and a second latch circuit latching the data blocks arranged in parallel simultaneously in response to a clock signal.

Abstract translation: 提供了一种通过使用具有不同定时的时钟信号和执行该方法的装置对数据进行多路复用的方法。 同时执行数据的存储和复用（或分割）。 该装置包括：第一锁存电路，其响应于不重叠的锁存控制信号并行输入串行输入的数据块;以及第二锁存电路，其响应于时钟信号同时锁存并行排列的数据块。

公开(公告)号：US08963448B2

公开(公告)日：2015-02-24

申请号：US13800077

申请日：2013-03-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyung Tae Kim ,  Soo Ik Cha ,  Jun Ho Song ,  Jin Chul Choi ,  Chul Ho Choi

IPC: H03F3/45 ,  G09G3/22 ,  H03F3/30 ,  G09G3/36

CPC classification number: H03F3/45179 ,  G09G3/22 ,  G09G3/3688 ,  G09G2310/0291 ,  H03F3/3022 ,  H03F3/45475 ,  H03F2203/45248 ,  H03F2203/45528

Abstract: An output buffer circuit includes an amplifier and a transmission circuit. The amplifier includes a plurality of inputs and an output. The inputs provide first input signals and second input signals to the amplifier. The output provides an output signal as a first input signal of the first input signals to the amplifier. The transmission circuit has an input coupled to the output of the amplifier and further has an output that provides a transmission circuit output signal as a second input signal of the second input signals to the amplifier.

Abstract translation: 输出缓冲电路包括放大器和发送电路。 放大器包括多个输入和输出。 输入端为放大器提供第一输入信号和第二输入信号。 该输出提供输出信号作为到放大器的第一输入信号的第一输入信号。 发送电路具有耦合到放大器的输出端的输入端，并且还具有输出，该输出端将作为第二输入信号的第二输入信号的发送电路输出信号提供给放大器。