公开(公告)号：US10580719B2

公开(公告)日：2020-03-03

申请号：US15143865

申请日：2016-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghun Kang ,  Kyoung-nam Ha ,  Hyungdong Kim ,  Jun-Phil Jung

IPC: G11C29/00 ,  H01L23/48 ,  G11C29/02 ,  G11C29/52 ,  G11C29/44 ,  G11C5/02 ,  G06F11/10 ,  G11C11/4093 ,  H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  G11C11/401

Abstract: The semiconductor memory device includes first group dies including at least one buffer die, and second group dies including a plurality of memory dies stacked on the first group dies and conveying data through a plurality of TSV lines. Here, at least one of the plurality of memory dies includes a first type ECC circuit which generates transmission parity bits using transmission data to be transmitted to the first group die, and the buffer die includes a second type ECC circuit which corrects, when a transmission error occurs in the transmission data received through the plurality of TSV lines, the transmission error using the transmission parity bits and generates error-corrected data.