公开(公告)号：US20140333346A1

公开(公告)日：2014-11-13

申请号：US14272975

申请日：2014-05-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhan BAE ,  Kee-won KWON ,  Kyoungho KIM ,  Jung Hoon CHUN ,  Youngsoo SOHN ,  Seok KIM

IPC: H03L7/087

CPC classification number: H03L7/0891 ,  H03D13/004 ,  H03L7/081 ,  H03L7/085 ,  H03L7/087 ,  H03L7/0995 ,  H03L7/104 ,  H03L7/107 ,  H03L7/1072

Abstract: A phase-rotating phase locked loop (PLL) may include first and second loops that share a loop filter and a voltage controlled oscillator in order to perform the operation of a phase-rotating PLL, the first and second loops configured to activate in response to an enable signal. The PLL may further include a phase frequency detection controller configured to provide the enable signal to the first and second loops in response to a transition of a coarse signal that may be applied as a digital code.

Abstract translation: 相位旋转锁相环（PLL）可以包括共享环路滤波器和压控振荡器的第一和第二回路，以便执行相位旋转PLL的操作，第一和第二回路被配置为响应于 一个使能信号。 PLL可以进一步包括相位频率检测控制器，其被配置为响应于作为数字代码应用的粗略信号的转变，向第一和第二环路提供使能信号。

公开(公告)号：US20230298663A1

公开(公告)日：2023-09-21

申请号：US17883546

申请日：2022-08-08

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  Research & Business Foundation SUNGKYUNKWAN UNIVERSITY

Inventor： Jung Hoon CHUN ,  Ji Ho SONG ,  Yoonmyung LEE ,  Ju A LEE

IPC: G11C11/54 ,  G11C13/00 ,  G06N3/06

CPC classification number: G11C11/54 ,  G11C13/004 ,  G06N3/061

Abstract: A neural network method and device are included, A neural network circuit includes a synaptic memory cell including a resistive memory element, which is disposed along an output line and which can have a first resistance value and a second resistance value as a resistance value, the synaptic memory cell generates a column signal, based on the resistance value of the resistive memory element and an input signal received via an input line, a reference memory cell including a reference memory element, which is disposed along a reference line and which has a resistance value that is a ratio of the first and second resistance values, the reference memory cell generates a reference signal, based on the resistance value of the reference memory element and the input signal, and an output circuit generates an output signal for the output line based on the column signal and the reference signal.

公开(公告)号：US20160315625A1

公开(公告)日：2016-10-27

申请号：US15179202

申请日：2016-06-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhan BAE ,  Kee-Won KWON ,  Kyungho KIM ,  Jung Hoon CHUN ,  Youngsoo SOHN ,  Seok KIM

IPC: H03L7/089 ,  H03L7/099

CPC classification number: H03L7/0891 ,  H03D13/004 ,  H03L7/081 ,  H03L7/085 ,  H03L7/087 ,  H03L7/0995 ,  H03L7/104 ,  H03L7/107 ,  H03L7/1072

Abstract: A phase-rotating phase locked loop (PLL) may include first and second loops that share a loop filter and a voltage controlled oscillator in order to perform the operation of a phase-rotating PLL, the first and second loops configured to activate in response to an enable signal. The PLL may further include a phase frequency detection controller configured to provide the enable signal to the first and second loops in response to a transition of a coarse signal that may be applied as a digital code.

Abstract translation: 相位旋转锁相环（PLL）可以包括共享环路滤波器和压控振荡器的第一和第二回路，以便执行相位旋转PLL的操作，第一和第二回路被配置为响应于 一个使能信号。 PLL可以进一步包括相位频率检测控制器，其被配置为响应于作为数字代码应用的粗略信号的转变，向第一和第二环路提供使能信号。