公开(公告)号：US20150009742A1

公开(公告)日：2015-01-08

申请号：US14223867

申请日：2014-03-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyu-Chang KANG ,  Jung-Bum SHIN ,  Chan-Yong LEE

IPC: G11C14/00 ,  G11C5/14 ,  G11C17/16

CPC classification number: G11C17/16 ,  G11C17/18 ,  G11C2029/0407 ,  G11C2029/4402

Abstract: Provided is a semiconductor memory device with improved fuse sensing reliability during a slow power-up operation. The semiconductor memory device may include a memory cell array including a normal memory cell array and a spare memory cell array; an anti-fuse circuit supplied with a first voltage and configured to store fail address information associated with a defective memory cell in the normal memory cell array and configured to sense the fail address information in response to a clock signal applied during a power-up period; and a fuse read circuit including a clock generator supplied with a second voltage, the fuse read circuit configured to detect respective levels of the first and second voltages during the power-up period to generate the clock signal and to read the sensed fail address information from the anti-fuse circuit in response to the clock signal.

Abstract translation: 提供了在慢速上电操作期间具有改进的熔丝感测可靠性的半导体存储器件。 半导体存储器件可以包括包括正常存储单元阵列和备用存储单元阵列的存储单元阵列; 提供有第一电压并被配置为存储与正常存储单元阵列中的有缺陷的存储器单元相关联的故障地址信息的反熔丝电路，并且被配置为响应于在上电周期期间施加的时钟信号来感测故障地址信息 ; 以及包括提供有第二电压的时钟发生器的熔丝读取电路，所述熔丝读取电路被配置为在上电周期期间检测第一和第二电压的相应电平，以产生时钟信号，并从 反熔丝电路响应于时钟信号。