公开(公告)号：US20190131516A1

公开(公告)日：2019-05-02

申请号：US15983255

申请日：2018-05-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-hwan PARK ,  Ju-hyun KIM ,  Se-chung OH ,  Dong-kyu LEE ,  Jung-min LEE ,  Kyung-il HONG

IPC: H01L43/02 ,  H01L43/12 ,  G11C11/16 ,  H01L27/22 ,  H01L23/538 ,  H01L23/532

Abstract: A variable resistance memory device includes a metal interconnection layer on a substrate, an interlayer insulating layer on the metal interconnection layer and defining a contact hole for exposing a portion of the metal interconnection layer, a barrier metal layer including a plurality of sub-barrier metal layers inside the contact hole, a plug metal layer on the barrier metal layer and burying the contact hole, and a variable resistance structure on the barrier metal layer and the plug metal layer.