公开(公告)号：US11955525B2

公开(公告)日：2024-04-09

申请号：US17941828

申请日：2022-09-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghwan Huh ,  Dongchan Kim ,  Dae Hyun Kim ,  Euiju Kim ,  Jisoo Lee

IPC: H01L29/423 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/4236 ,  H01L21/76877 ,  H01L21/823437 ,  H01L21/82345 ,  H01L29/42364 ,  H01L29/4916 ,  H01L29/518 ,  H01L29/78 ,  H01L29/7827

Abstract: A semiconductor device includes a substrate, a gate trench in the substrate, a gate insulating film in the gate trench, a titanium nitride (TiN)-lower gate electrode film on the gate insulating film, the titanium nitride (TiN)-lower gate electrode film including a top surface, a first side surface, and a second side surface opposite the first side surface, a polysilicon-upper gate electrode film on the titanium nitride (TiN)-lower gate electrode film, and a gate capping film on the polysilicon-upper gate electrode film. A center portion of the top surface of the titanium nitride (TiN)-lower gate electrode film overlaps a center portion of the polysilicon-upper gate electrode film in a direction that is perpendicular to a top surface of the substrate, and each of the first side surface and the second side surface of the titanium nitride (TiN)-lower gate electrode film is connected to the gate insulating film.

公开(公告)号：US20240244830A1

公开(公告)日：2024-07-18

申请号：US18530559

申请日：2023-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoojin Jeong ,  Junghwan Huh

IPC: H10B12/00

CPC classification number: H10B12/34 ,  H10B12/053 ,  H10B12/315

Abstract: A semiconductor device includes a substrate having an active region defined by an isolation layer, a word line crossing the active region and extending, within the substrate, in a first horizontal direction inside a word line trench, the word line trench being formed in the substrate and including a first sub word line trench and a second sub word line trench. A width, in the first horizontal direction, of a lower surface of the first sub word line trench is greater than a width, in the first horizontal direction, of a lower surface of the second sub word line trench, and a first distance between the lower surface of the first sub word line trench and an upper surface of the active region is less than a second distance between the lower surface of the second sub word line trench and the upper surface of the active region.

公开(公告)号：US11462623B2

公开(公告)日：2022-10-04

申请号：US17222474

申请日：2021-04-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghwan Huh ,  Dongchan Kim ,  Dae Hyun Kim ,  Euiju Kim ,  Jisoo Lee

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/51 ,  H01L29/49

Abstract: A semiconductor device includes a substrate including an active region, a gate trench disposed in the substrate and crossing the active region; a gate dielectric layer disposed in the gate trench; a first gate electrode disposed on the gate dielectric layer and including center and edge portions; a second gate electrode disposed on the first gate electrode; a gate capping insulating layer disposed on the second gate electrode and filling the gate trench; and first and second impurity regions disposed in the substrate opposite to each other with respect to the gate trench. A top surface of each of the center and edge portions contacts a bottom surface of the second gate electrode. The top surface of the second gate electrode is concave. The bottom surface of the gate capping insulating layer is convex, and a side surface of the gate capping insulating layer contacts the gate dielectric layer.

公开(公告)号：US10985255B2

公开(公告)日：2021-04-20

申请号：US16523529

申请日：2019-07-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghwan Huh ,  Dongchan Kim ,  Dae Hyun Kim ,  Euiju Kim ,  Jisoo Lee

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/51 ,  H01L29/49

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a gate trench crossing an active region, and a gate structure in the gate trench. The gate structure includes a gate dielectric layer disposed on an inner wall of the gate trench, a gate electrode disposed on the gate electric layer and partially filling the gate trench, a gate capping insulating layer disposed on the gate electrode, and a gap-fill insulating layer disposed in the gate trench and disposed on the gate capping insulating layer. The gate capping insulating layer includes a material formed by oxidizing a portion of the gate electrode, nitriding the portion of the gate electrode, or oxidizing and nitriding the portion of the gate electrode.