公开(公告)号：US20230292489A1

公开(公告)日：2023-09-14

申请号：US17960578

申请日：2022-10-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungoo KANG ,  Jinsu LEE

IPC: H01L27/108

CPC classification number: H01L27/10814 ,  H01L27/10852

Abstract: Provided is a semiconductor device. The semiconductor device includes a lower structure; a lower electrode on the lower structure; a dielectric layer on the lower electrode; and an upper electrode on the dielectric layer, wherein the lower electrode includes a bending reducing layer and a dielectric constant-increasing layer between the bending reducing layer and the dielectric layer, the dielectric constant-increasing layer is configured to increase a dielectric constant of the dielectric layer, and an elastic modulus of the bending reducing layer is greater than an elastic modulus of the dielectric constant-increasing layer.

公开(公告)号：US20220336578A1

公开(公告)日：2022-10-20

申请号：US17857383

申请日：2022-07-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gihee CHO ,  Sangyeol KANG ,  Jungoo KANG ,  Taekyun KIM ,  Jiwoon PARK ,  Sanghyuck AHN ,  Jin-Su LEE ,  Hyun-Suk LEE ,  Hongsik CHAE

IPC: H01L49/02 ,  H01L27/108

Abstract: A semiconductor device and a method of manufacturing the same, the device including a plurality of lower electrodes on a semiconductor substrate; a support pattern connecting the lower electrodes at sides of the lower electrodes; and a dielectric layer covering the lower electrodes and the support pattern, wherein each of the plurality of lower electrodes includes a pillar portion extending in a vertical direction perpendicular to a top surface of the semiconductor substrate; and a protrusion protruding from a sidewall of the pillar portion so as to be in contact with the support pattern, the pillar portion includes a conductive material, the protrusion includes a same conductive material as the pillar portion and is further doped with impurities.

公开(公告)号：US20220216209A1

公开(公告)日：2022-07-07

申请号：US17701866

申请日：2022-03-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gihee CHO ,  Jungoo KANG ,  Hyun-Suk LEE ,  Sanghyuck AHN

IPC: H01L27/108 ,  H01L49/02 ,  H01L21/02

Abstract: A semiconductor memory device includes a capacitor having a bottom electrode and a top electrode, a dielectric layer between the bottom and top electrodes, and an interface layer between the top electrode and the dielectric layer, the interface layer including a metal oxide and an additional constituent at a grain boundary of the interface layer.

公开(公告)号：US20220037461A1

公开(公告)日：2022-02-03

申请号：US17189700

申请日：2021-03-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gihee CHO ,  Sangyeol KANG ,  Jungoo KANG ,  Taekyun KIM ,  Jiwoon PARK ,  Sanghyuck AHN ,  Jin-Su LEE ,  Hyun-Suk LEE ,  Hongsik CHAE

IPC: H01L49/02 ,  H01L27/108

Abstract: A semiconductor device and a method of manufacturing the same, the device including a plurality of lower electrodes on a semiconductor substrate; a support pattern connecting the lower electrodes at sides of the lower electrodes; and a dielectric layer covering the lower electrodes and the support pattern, wherein each of the plurality of lower electrodes includes a pillar portion extending in a vertical direction perpendicular to a top surface of the semiconductor substrate; and a protrusion protruding from a sidewall of the pillar portion so as to be in contact with the support pattern, the pillar portion includes a conductive material, the protrusion includes a same conductive material as the pillar portion and is further doped with impurities.

公开(公告)号：US20230397404A1

公开(公告)日：2023-12-07

申请号：US18138311

申请日：2023-04-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungoo KANG ,  Dayeon NAM ,  Sungjoon YOON ,  Donggeon LEE

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/033

Abstract: An integrated circuit device includes: a capacitor structure, wherein the capacitor structure includes: a lower electrode arranged on a substrate, wherein the lower electrode includes an electrode layer extending in a direction substantially perpendicular to an upper surface of the substrate, wherein the electrode layer includes niobium nitride; a supporter arranged on a sidewall of the lower electrode; a dielectric layer arranged on the lower electrode and the supporter; a first interface layer arranged between a sidewall of the lower electrode and the dielectric layer and between a top surface of the lower electrode and the dielectric layer, wherein the first interface layer includes a conductive metal nitride; and an upper electrode arranged on the dielectric layer, wherein the upper electrode covers the lower electrode and includes niobium nitride.

公开(公告)号：US20210134803A1

公开(公告)日：2021-05-06

申请号：US16903586

申请日：2020-06-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gihee CHO ,  Jungoo KANG ,  Hyun-Suk LEE ,  Sanghyuck AHN

IPC: H01L27/108 ,  H01L21/02 ,  H01L49/02

Abstract: A semiconductor memory device includes a capacitor having a bottom electrode and a top electrode, a dielectric layer between the bottom and top electrodes, and an interface layer between the top electrode and the dielectric layer, the interface layer including a metal oxide and an additional constituent at a grain boundary of the interface layer.