公开(公告)号：US20220310541A1

公开(公告)日：2022-09-29

申请号：US17541719

申请日：2021-12-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoonjoo NA ,  Jungseob SO ,  Taeseong KIM ,  Sohye CHO ,  Sonkwan HWANG

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: The semiconductor device includes a lower chip structure including a peripheral circuit, a first memory chip structure on the lower chip structure, and a second memory chip structure on the first memory chip structure. The first memory chip structure includes a first stack structure and a first vertical memory structure. The first stack structure includes first gate lines stacked in a vertical direction and extending in a first horizontal direction. The first vertical memory structure penetrates through the first gate lines in the vertical direction. The second memory chip structure includes a second stack structure and a second vertical memory structure. The second stack structure includes second gate lines stacked in the vertical direction and extending in a second horizontal direction, perpendicular to the first horizontal direction. The second vertical memory structure penetrates through the second gate lines in the vertical direction.

公开(公告)号：US20250062262A1

公开(公告)日：2025-02-20

申请号：US18934371

申请日：2024-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoonjoo NA ,  Jungseob SO ,  Taeseong KIM ,  Sohye CHO ,  Sonkwan HWANG

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: The semiconductor device includes a lower chip structure including a peripheral circuit, a first memory chip structure on the lower chip structure, and a second memory chip structure on the first memory chip structure. The first memory chip structure includes a first stack structure and a first vertical memory structure. The first stack structure includes first gate lines stacked in a vertical direction and extending in a first horizontal direction. The first vertical memory structure penetrates through the first gate lines in the vertical direction. The second memory chip structure includes a second stack structure and a second vertical memory structure. The second stack structure includes second gate lines stacked in the vertical direction and extending in a second horizontal direction, perpendicular to the first horizontal direction. The second vertical memory structure penetrates through the second gate lines in the vertical direction.