公开(公告)号：US20220310541A1

公开(公告)日：2022-09-29

申请号：US17541719

申请日：2021-12-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoonjoo NA ,  Jungseob SO ,  Taeseong KIM ,  Sohye CHO ,  Sonkwan HWANG

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: The semiconductor device includes a lower chip structure including a peripheral circuit, a first memory chip structure on the lower chip structure, and a second memory chip structure on the first memory chip structure. The first memory chip structure includes a first stack structure and a first vertical memory structure. The first stack structure includes first gate lines stacked in a vertical direction and extending in a first horizontal direction. The first vertical memory structure penetrates through the first gate lines in the vertical direction. The second memory chip structure includes a second stack structure and a second vertical memory structure. The second stack structure includes second gate lines stacked in the vertical direction and extending in a second horizontal direction, perpendicular to the first horizontal direction. The second vertical memory structure penetrates through the second gate lines in the vertical direction.

公开(公告)号：US20230253293A1

公开(公告)日：2023-08-10

申请号：US18075535

申请日：2022-12-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sohye CHO ,  Kwangjin MOON ,  Hojin LEE

IPC: H01L23/48 ,  H01L29/423 ,  H01L29/08 ,  H01L29/06 ,  H01L29/786 ,  H01L29/775

CPC classification number: H01L23/481 ,  H01L29/42392 ,  H01L29/0847 ,  H01L29/0673 ,  H01L29/78696 ,  H01L29/775

Abstract: A semiconductor device includes a first semiconductor substrate having a protruding active pattern, a gate structure, a source/drain region in the active pattern on a side of the gate structure, an interlayer insulating layer on the source/drain region, a contact structure connected to the source/drain region through the interlayer insulating layer, a through-via structure electrically connected to the contact structure and passing through the interlayer insulating layer and the first semiconductor substrate, a first bonding structure including a first insulating layer on the first semiconductor substrate and a first connection pad in the first insulating layer, a second bonding structure on the first bonding structure and including a second insulating layer bonded to the first insulating layer and a second connection pad in the second insulating layer and bonded to the first connection pad, and a second semiconductor substrate disposed on the second bonding structure.

公开(公告)号：US20240153883A1

公开(公告)日：2024-05-09

申请号：US18387729

申请日：2023-11-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seunghoon HAN ,  Doowon KWON ,  Taeyeong KIM ,  Minho JANG ,  Sohye CHO ,  Haesung KIM ,  Hyeonsoo PARK

IPC: H01L23/544 ,  H01L21/66

CPC classification number: H01L23/544 ,  H01L22/12 ,  H01L2223/54426

Abstract: Provided is a device including a substrate and an overlay target structure provided on the substrate, the overlay target structure includes a first alignment key having a plurality of line masks having a first width and arranged at a first pitch, a second alignment key having a plurality of line masks having a second width and arranged at a second pitch, and a nanostructure layer arranged between the first alignment key and the second alignment key, and including a plurality of nanostructures having widths less than or equal to the first width and the second width, and arranged at a pitch less than the first pitch and the second pitch.

公开(公告)号：US20210305130A1

公开(公告)日：2021-09-30

申请号：US17036145

申请日：2020-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sohye CHO ,  Pilkyu KANG ,  Kwangjin MOON ,  Taeseong KIM

IPC: H01L23/48 ,  H01L23/528 ,  H01L27/11 ,  H01L21/768

Abstract: An integrated circuit semiconductor device includes a substrate including a first surface and a second surface opposite the first surface, a trench in the substrate, the trench extending from the first surface of the substrate toward the second surface of the substrate, a through silicon via (TSV) landing part in the trench, the TSV landing part having a first portion spaced apart from the first surface of the substrate, and a second portion between the first portion and the first surface of the substrate, the first portion being wider than the second portion, a TSV hole in the substrate, the TSV hole extending from the second surface of the substrate and aligned with a bottom surface of the TSV landing part, and a TSV in the TSV hole and in contact with the bottom surface of the TSV landing part.

公开(公告)号：US20250062262A1

公开(公告)日：2025-02-20

申请号：US18934371

申请日：2024-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoonjoo NA ,  Jungseob SO ,  Taeseong KIM ,  Sohye CHO ,  Sonkwan HWANG

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: The semiconductor device includes a lower chip structure including a peripheral circuit, a first memory chip structure on the lower chip structure, and a second memory chip structure on the first memory chip structure. The first memory chip structure includes a first stack structure and a first vertical memory structure. The first stack structure includes first gate lines stacked in a vertical direction and extending in a first horizontal direction. The first vertical memory structure penetrates through the first gate lines in the vertical direction. The second memory chip structure includes a second stack structure and a second vertical memory structure. The second stack structure includes second gate lines stacked in the vertical direction and extending in a second horizontal direction, perpendicular to the first horizontal direction. The second vertical memory structure penetrates through the second gate lines in the vertical direction.