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公开(公告)号：US20220310541A1
公开(公告)日：2022-09-29
申请号：US17541719
申请日：2021-12-03
发明人： Hoonjoo NA , Jungseob SO , Taeseong KIM , Sohye CHO , Sonkwan HWANG
IPC分类号： H01L23/00 , H01L25/065 , H01L25/18
摘要： The semiconductor device includes a lower chip structure including a peripheral circuit, a first memory chip structure on the lower chip structure, and a second memory chip structure on the first memory chip structure. The first memory chip structure includes a first stack structure and a first vertical memory structure. The first stack structure includes first gate lines stacked in a vertical direction and extending in a first horizontal direction. The first vertical memory structure penetrates through the first gate lines in the vertical direction. The second memory chip structure includes a second stack structure and a second vertical memory structure. The second stack structure includes second gate lines stacked in the vertical direction and extending in a second horizontal direction, perpendicular to the first horizontal direction. The second vertical memory structure penetrates through the second gate lines in the vertical direction.
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公开(公告)号：US20240071841A1
公开(公告)日：2024-02-29
申请号：US18302401
申请日：2023-04-18
发明人： Sumin PARK , Taeseong KIM , Jaehyung PARK , Kyuha LEE , Yeojin LEE , Kwangjin MOON , Hojin LEE
IPC分类号： H01L21/66 , B24B37/013 , G06F30/392 , H01L23/00
CPC分类号： H01L22/20 , B24B37/013 , G06F30/392 , H01L22/32 , H01L24/03 , H01L24/05 , H01L2224/03845 , H01L2224/05571 , H01L2224/05647
摘要： In a manufacturing method of a wafer, the method including: an operation of preparing a wafer including a semiconductor chip region and a test region, measuring a measurement region included in the test region with an atomic force microscope (AFM), the measurement region including a plurality of metal lines having a constant line width and a constant pitch; determining a surface roughness value of the test region based on a result of the measuring of the measurement region; determining a step difference value of the metal lines of the test region based on the surface roughness value; and determining a step difference value of bonding pads in the semiconductor chip region based on the step difference value of the metal lines.
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公开(公告)号：US20210305130A1
公开(公告)日：2021-09-30
申请号：US17036145
申请日：2020-09-29
发明人： Sohye CHO , Pilkyu KANG , Kwangjin MOON , Taeseong KIM
IPC分类号： H01L23/48 , H01L23/528 , H01L27/11 , H01L21/768
摘要： An integrated circuit semiconductor device includes a substrate including a first surface and a second surface opposite the first surface, a trench in the substrate, the trench extending from the first surface of the substrate toward the second surface of the substrate, a through silicon via (TSV) landing part in the trench, the TSV landing part having a first portion spaced apart from the first surface of the substrate, and a second portion between the first portion and the first surface of the substrate, the first portion being wider than the second portion, a TSV hole in the substrate, the TSV hole extending from the second surface of the substrate and aligned with a bottom surface of the TSV landing part, and a TSV in the TSV hole and in contact with the bottom surface of the TSV landing part.
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公开(公告)号：US20220406740A1
公开(公告)日：2022-12-22
申请号：US17544081
申请日：2021-12-07
发明人： Taeyeong KIM , Taeseong KIM , Kwangjin MOON , Hyungjun JEON
IPC分类号： H01L23/00 , H01L27/146 , H01L23/488
摘要： A semiconductor device including a first structure including a first dielectric layer and a first conductive pattern in the first dielectric layer, the first conductive pattern including a first conductive material and a first bonding enhancement material; a second structure including a second dielectric layer and a second conductive pattern in the second dielectric layer, the second dielectric layer directly contacting the first dielectric layer, the second conductive pattern directly contacting the first conductive pattern; and a first bonding enhancement layer between the first conductive pattern and the second dielectric layer, wherein the first bonding enhancement layer includes the first bonding enhancement material or a material of the second dielectric layer, and the first bonding enhancement material includes a material having a higher bonding force to the material of the second dielectric layer than a bonding force of the first conductive material to the material of the second dielectric layer.
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公开(公告)号：US20220310485A1
公开(公告)日：2022-09-29
申请号：US17514218
申请日：2021-10-29
发明人： Sonkwan HWANG , Taeseong KIM , Hoonjoo NA , Kwangjin MOON , Hyungjun JEON
IPC分类号： H01L23/48 , H01L23/528 , H01L27/088 , H01L25/065 , H01L21/768
摘要： A semiconductor device including a semiconductor substrate, an integrated circuit layer on the semiconductor substrate, first to nth metal wiring layers (where n is a positive integer) sequentially stacked on the semiconductor substrate and the integrated circuit layer, a first through via structure extending in a vertical direction toward the semiconductor substrate from a first via connection metal wiring layer, which is one of the second to nth metal wiring layers other than the first metal wiring layer, and passing through the semiconductor substrate, and a second through via structure being apart from the first through via structure, extending in a vertical direction toward the semiconductor substrate from a second via connection metal wiring layer, which is one of the second to nth metal wiring layers other than the first metal wiring layer, and passing through the semiconductor substrate may be provided.
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公开(公告)号：US20230361004A1
公开(公告)日：2023-11-09
申请号：US18354068
申请日：2023-07-18
发明人： Sonkwan HWANG , Taeseong KIM , Hoonjoo NA , Kwangjin MOON , Hyungjun JEON
IPC分类号： H01L23/48 , H01L27/088 , H01L25/065 , H01L21/768 , H01L23/528
CPC分类号： H01L23/481 , H01L27/0886 , H01L25/0657 , H01L21/76898 , H01L23/528 , H01L2224/0603 , H01L2225/06513 , H01L2225/06544 , H01L24/06
摘要： A semiconductor device including a semiconductor substrate, an integrated circuit layer on the semiconductor substrate, first to nth metal wiring layers (where n is a positive integer) sequentially stacked on the semiconductor substrate and the integrated circuit layer, a first through via structure extending in a vertical direction toward the semiconductor substrate from a first via connection metal wiring layer, which is one of the second to nth metal wiring layers other than the first metal wiring layer, and passing through the semiconductor substrate, and a second through via structure being apart from the first through via structure, extending in a vertical direction toward the semiconductor substrate from a second via connection metal wiring layer, which is one of the second to nth metal wiring layers other than the first metal wiring layer, and passing through the semiconductor substrate may be provided.
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公开(公告)号：US20200066682A1
公开(公告)日：2020-02-27
申请号：US16408891
申请日：2019-05-10
发明人： Taeseong KIM , Kwangjin MOON , Hyoju KIM , Junhong MIN , Hakseung LEE
IPC分类号： H01L25/065 , H01L23/00 , H01L25/00 , H01L21/768
摘要： Disclosed are semiconductor packages and methods of manufacturing the same. The semiconductor package comprises a substrate, a first unit structure attached to the substrate, and a second unit structure attached to the first unit structure. Each of the first and second unit structures comprises an adhesive layer, a lower semiconductor chip on the adhesive layer, an upper semiconductor chip on and in contact with the lower semiconductor chip, and a plurality of vias penetrating the upper semiconductor chip and connecting with the lower and upper semiconductor chips.
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8.发明申请公开(公告)号：US20200343291A1
公开(公告)日：2020-10-29
申请号：US16926924
申请日：2020-07-13
发明人： Yi Koan HONG , Taeseong KIM
IPC分类号： H01L27/146 , H01L21/768 , H01L23/00 , H01L23/48
摘要： A semiconductor device including a first structure including a first conductive pattern, the first conductive pattern exposed on an upper portion of the first structure, a mold layer covering the first conductive pattern, a second structure on the mold layer, and a through via penetrating the second structure and the mold layer, the through via electrically connected to the first conductive pattern, the through via including a first via segment in the second structure and a second via segment in the mold layer, the second via segment connected to the first via segment, an upper portion of the second via segment having a first width and a middle portion of the second via segment having a second width greater than the first width may be provided.
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