公开(公告)号：US20250068225A1

公开(公告)日：2025-02-27

申请号：US18947457

申请日：2024-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhee YOO ,  Jaehyun KIM ,  Jingyu AHN ,  Wooil KIM ,  Manhwee JO

IPC: G06F1/3234 ,  G11C7/22

Abstract: A system on chip (SoC) and an application processor are provided. The SoC includes a memory controller configured to control a memory; a plurality of function modules configured to access the memory through a memory interface; a system interconnect circuit configured to operate based on a first clock signal and connect the memory interface and the plurality of function modules; and a power controller configured to control the first clock signal to be periodically gated, and control the memory to operate in a lower-power mode during a period in which the first clock signal is gated.

公开(公告)号：US20240111686A1

公开(公告)日：2024-04-04

申请号：US18473917

申请日：2023-09-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhee YOO ,  Seunghun KIM

IPC: G06F12/1009 ,  G06F12/14

CPC classification number: G06F12/1009 ,  G06F12/1408 ,  G06F12/1425

Abstract: An application processor, a System-on-a-Chip (SoC), and a method of operating the same are provided. The SoC includes a first processor outputting a first access address, a system bus configured to transmit an access address to a memory if the access address, which is received from the first processor corresponds to a physical address area of the memory, and to transmit the access address to other processing circuits other than the memory if the access address corresponds to a shadow physical address area other than the physical address area of the memory, and a sub-processing circuit receiving the first access address from the first processor via the system bus, converting the first access address into a second access address corresponding to the physical address area, and transmitting the second access address to the system bus to access the memory.

公开(公告)号：US20200210337A1

公开(公告)日：2020-07-02

申请号：US16289650

申请日：2019-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hien LE ,  Junhee YOO ,  Vikas Kumar SINHA ,  Robert BELL ,  Matthew Derrick GARRETT

IPC: G06F12/0815 ,  G06F12/0882 ,  G06F13/16 ,  G06F3/06

Abstract: A system and a method provide a memory-access technique that effectively parallelizes DRAM operations and coherency operations to reduce memory-access latency. The system may include a memory controller, an interconnect and a processor. The interconnect may be coupled to the memory controller. The processor may be coupled to the memory controller through a first path and a second path in which the first path is through the interconnect and the second path bypasses the interconnect. The processor may be configured to send substantially concurrently a memory access request to the memory controller via the first path and send a page activation request or a hint request to the memory controller via the second path so that the DRAM access operations appear to be masked, or hidden by the coherency operations.