公开(公告)号：US20200035520A1

公开(公告)日：2020-01-30

申请号：US16046983

申请日：2018-07-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Rodolfo MARTINEZ ,  Robert BELL ,  Robert STEBBINS

IPC: H01L21/67 ,  F16M11/16 ,  F16M11/42 ,  H01L21/687 ,  H05B6/10

Abstract: A stand for a heater pedestal with a base member and a support member detachably coupled to the base member, the support member having a plurality of ring members and at least one spacer member extending vertically from the base member, a ring member separated from another ring member by a spacer member, a ring member having an aperture which extends through the ring member in a horizontal direction, the at least one spacer member forming at least one opening between two corresponding ring members, and the ring member furthest from the base member configured to support a heater pedestal, and the apertures of the ring members of the support member being configured to receive a susceptor of the heater pedestal.

公开(公告)号：US20200210337A1

公开(公告)日：2020-07-02

申请号：US16289650

申请日：2019-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hien LE ,  Junhee YOO ,  Vikas Kumar SINHA ,  Robert BELL ,  Matthew Derrick GARRETT

IPC: G06F12/0815 ,  G06F12/0882 ,  G06F13/16 ,  G06F3/06

Abstract: A system and a method provide a memory-access technique that effectively parallelizes DRAM operations and coherency operations to reduce memory-access latency. The system may include a memory controller, an interconnect and a processor. The interconnect may be coupled to the memory controller. The processor may be coupled to the memory controller through a first path and a second path in which the first path is through the interconnect and the second path bypasses the interconnect. The processor may be configured to send substantially concurrently a memory access request to the memory controller via the first path and send a page activation request or a hint request to the memory controller via the second path so that the DRAM access operations appear to be masked, or hidden by the coherency operations.

公开(公告)号：US20190214283A1

公开(公告)日：2019-07-11

申请号：US15867658

申请日：2018-01-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Matthew JESTER ,  Robert BELL ,  Robert STEBBINS ,  Soren SPRISSLER

IPC: H01L21/67 ,  B66F11/00

CPC classification number: H01L21/67196 ,  B66F11/00

Abstract: A process system of performing a fabrication process on a wafer includes a wafer storage cassette, process chambers, a transfer chamber having a body and a lid that detachably covers the body, a frame configured to support the transfer chamber, and a lifting tool connected to the lid and extended from the lid over a portion of the frame. The body of the transfer chamber is connected to the wafer storage cassette and the plurality of process chambers so that the wafer is transferred from the wafer storage cassette through the body of the transfer chamber to one of the process chambers.