公开(公告)号：US20230395482A1

公开(公告)日：2023-12-07

申请号：US18060812

申请日：2022-12-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungjoo KIM ,  Yongkwan LEE ,  Seung Hwan KIM ,  Jongwan KIM ,  Junwoo PARK ,  Taejun JEON ,  Junhyeung JO

IPC: H01L23/498 ,  H01L25/16 ,  H01G4/228 ,  H01L23/538

CPC classification number: H01L23/49838 ,  H01L25/16 ,  H01L25/162 ,  H01G4/228 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5389 ,  H01G4/08

Abstract: A semiconductor package including a dielectric layer on a substrate and having an opening that partially exposes a top surface of the substrate, a capacitor chip on the substrate and in the opening of the dielectric layer, connection terminals between the substrate and the capacitor chip and connecting the substrate and the capacitor chip to each other, dielectric patches on the substrate and in the opening of the dielectric layer, and an under-fill filling a space between the substrate and the capacitor chip may be provided. The space between the substrate and the capacitor chip includes a first region, a second region, and a third region between the first and second regions. The connection terminals are on the first region and the second region. The dielectric patches are on the third region.