公开(公告)号：US20240096748A1

公开(公告)日：2024-03-21

申请号：US18453026

申请日：2023-08-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taejun JEON ,  Yongkwan LEE ,  Gyuhyeong KIM ,  Seunghwan KIM ,  Jongwan KIM ,  Junwoo PARK

IPC: H01L23/473 ,  H01L23/00

CPC classification number: H01L23/473 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16052 ,  H01L2224/16175 ,  H01L2224/16225 ,  H01L2224/32221 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/17151 ,  H01L2924/172 ,  H01L2924/177

Abstract: A chip protection device includes a protection frame extending around side surfaces of a semiconductor chip mounted on a substrate. The protection frame includes a plurality of side walls, each wall facing and spaced apart from a respective side surface of the semiconductor chip, and a plurality of upper walls, each upper wall extending inward from an upper portion of a respective side wall toward the semiconductor chip. A plurality of apertures are formed through the side walls and through which a fluid enters and exits. The protection frame defines an inner space in which the fluid can flow via the plurality of apertures. Heat from the side surfaces of the semiconductor chip is transferred to the fluid in the inner space.

公开(公告)号：US20250046663A1

公开(公告)日：2025-02-06

申请号：US18667258

申请日：2024-05-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taejun JEON ,  Yongkwan LEE ,  Seunghwan KIM ,  Junwoo PARK ,  Gyuhyeong KIM

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/64

Abstract: A semiconductor package includes a package substrate having a first region, a second region and third region sequentially arranged from a first side portion to a second side portion thereof. The second region has a chip mounting region in a central region. A semiconductor chip is disposed in the chip mounting region and is mounted on a plurality of substrate pads of the package substrate. A pair of first flow control structures is disposed in the first region and is arranged symmetrically on both sides along a center line passing through a center of the chip mounting region. At least one pair of second flow control structures is disposed in the second region of the package substrate and is arranged symmetrically on both sides of the chip mounting region. A molding member is on the package substrate and fills a gap between the semiconductor chip and the package substrate.

公开(公告)号：US20240420972A1

公开(公告)日：2024-12-19

申请号：US18402567

申请日：2024-01-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taejun JEON ,  Yongkwan LEE ,  Gyuhyeong KIM ,  Seung Hwan KIM ,  Jongwan KIM ,  Junwoo PARK

IPC: H01L21/67 ,  H01L21/56

Abstract: Disclosed are semiconductor molding apparatuses and compression molding methods. The semiconductor molding apparatus comprises an upper mold capable of supporting a substrate, a lower mold that provides a first cavity capable of being filled with a resin, a guide member that provides a second cavity to be filled with the resin and vertically penetrates the lower mold, and a guide lift capable of driving the guide member to vertically move. The lower mold includes a base plate that extends in a horizontal direction and a sidewall member that upwardly extends from the base plate. The guide lift drives the guide member to vertically move such that a top surface of the guide member moves between a top surface of the base plate and a top surface of the sidewall member.

公开(公告)号：US20230127641A1

公开(公告)日：2023-04-27

申请号：US17862662

申请日：2022-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunghwan KIM ,  Kyonghwan KOH ,  Jungjoo KIM ,  Jongwan KIM ,  Junwoo PARK ,  Hyunggil BAEK ,  Yongkwan LEE ,  Dongju JANG ,  Taejun JEON

IPC: H01L21/56 ,  H01L23/00 ,  H01L25/10 ,  H01L23/498 ,  H01L23/31

Abstract: A method of manufacturing a semiconductor package may include providing a substrate having first and second cutting regions respectively provided along first and second side portions opposite to each other and a mounting region between the first and second cutting regions is provided, disposing at least one semiconductor chip on the mounting region, forming a molding member on the substrate, and removing a dummy curl portion and at least portions of dummy runner portions from the molding member. The molding member may include a sealing portion, the dummy curl portion provided outside the second side portion of the substrate, and the plurality of dummy runner portions on the second cutting region to connect the sealing portion and the dummy curl portion. The substrate may include adhesion reducing pads in the second cutting region, which may contact the dummy runner portions respectively.

公开(公告)号：US20240079342A1

公开(公告)日：2024-03-07

申请号：US18195429

申请日：2023-05-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taejun JEON ,  Junwoo PARK ,  Yongkwan LEE ,  Seung Hwan KIM ,  Jongwan KIM

IPC: H01L23/544 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10 ,  H10B80/00

CPC classification number: H01L23/544 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/5385 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H10B80/00 ,  H01L24/16 ,  H01L2223/54426 ,  H01L2224/16145 ,  H01L2224/16227

Abstract: A semiconductor package including: a first substrate; a first semiconductor chip and a second substrate horizontally spaced apart from each other on the first substrate; and a molding layer on the first substrate, the first semiconductor chip and the second substrate, wherein a thickness of the first semiconductor chip is greater than a thickness of the second substrate, wherein the molding layer exposes a top surface of the second substrate, and wherein the second substrate has fiducial marks exposed on the top surface of the second substrate.

公开(公告)号：US20230395482A1

公开(公告)日：2023-12-07

申请号：US18060812

申请日：2022-12-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungjoo KIM ,  Yongkwan LEE ,  Seung Hwan KIM ,  Jongwan KIM ,  Junwoo PARK ,  Taejun JEON ,  Junhyeung JO

IPC: H01L23/498 ,  H01L25/16 ,  H01G4/228 ,  H01L23/538

CPC classification number: H01L23/49838 ,  H01L25/16 ,  H01L25/162 ,  H01G4/228 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5389 ,  H01G4/08

Abstract: A semiconductor package including a dielectric layer on a substrate and having an opening that partially exposes a top surface of the substrate, a capacitor chip on the substrate and in the opening of the dielectric layer, connection terminals between the substrate and the capacitor chip and connecting the substrate and the capacitor chip to each other, dielectric patches on the substrate and in the opening of the dielectric layer, and an under-fill filling a space between the substrate and the capacitor chip may be provided. The space between the substrate and the capacitor chip includes a first region, a second region, and a third region between the first and second regions. The connection terminals are on the first region and the second region. The dielectric patches are on the third region.

公开(公告)号：US20230147815A1

公开(公告)日：2023-05-11

申请号：US17432404

申请日：2020-02-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghyun CHO ,  Jinwoo JANG ,  Junwoo PARK ,  Youngsok SONG ,  Rakyoung YOON

IPC: H04W12/069 ,  H04W12/71 ,  H04W12/033

CPC classification number: H04W12/069 ,  H04W12/033 ,  H04W12/71

Abstract: An electronic device and an authentication method in the electronic device are provided. The electronic device includes a communication circuit; and at least one processor operatively connected to the communication circuit. The at least one processor may be configured to confirm the occurrence of an authentication event for communication-related security data; in response to the occurrence of the authentication event, confirm at least one piece of communication-related security data stored in a designated area of the electronic device; transmit a certificate request message including the at least one confirmed piece of communication-related security data, to an authentication server by means of the communication circuit; receive a certificate, generated based on at least one communication-related security data included in the transmitted certificate request message from the authentication server through the communication circuit; and authenticate use authority of the communication-related security data, based on the received certificate.

公开(公告)号：US20230018495A1

公开(公告)日：2023-01-19

申请号：US17841826

申请日：2022-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghyun CHO ,  Hanjae JEONG ,  Hyunchool CHUNG ,  Seungjoo NA ,  Youcheol MOON ,  Junwoo PARK ,  Jisun LEE ,  Sangyoung JU

IPC: H04W8/18 ,  H04W8/24 ,  H04W12/71 ,  H04W12/72

Abstract: An electronic device according to an embodiment of the disclosure may include a communication module, a subscriber identification module, and at least one processor. The at least one processor may identify identification information of the subscriber identification module stored in the subscriber identification module when the subscriber identification module is identified as being first inserted, may configure a network service provider based on the identified identification information, may generate a signature by using lock information of the subscriber identification module, may identify network lock information when the signature is identified as being valid, and may set up a network lock function of the communication module based on the identified network lock information.

公开(公告)号：US20190067258A1

公开(公告)日：2019-02-28

申请号：US15960698

申请日：2018-04-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yun-Young KIM ,  PYOUNGWAN KIM ,  HYUNKI KIM ,  Junwoo PARK ,  Sangsoo KIM ,  Seung Hwan KIM ,  Sung-Kyu PARK ,  Insup SHIN

IPC: H01L25/11 ,  H01L25/00

CPC classification number: H01L25/117 ,  H01L21/561 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2225/1082 ,  H01L2225/1094 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2224/81

Abstract: Disclosed are a semiconductor package and a method of fabricating the same. The semiconductor package comprises a lower semiconductor chip on a lower substrate, a lower molding layer covering the lower semiconductor chip on the lower substrate and including a molding cavity that extends toward the lower semiconductor chip from a top surface of the lower molding layer, an interposer substrate on the top surface of the lower molding layer and including a substrate opening that penetrates the interposer substrate and overlaps the molding cavity, and an upper package on the interposer substrate. The molding cavity has a floor surface spaced apart from the upper package across a substantially hollow space.