公开(公告)号：US20190278511A1

公开(公告)日：2019-09-12

申请号：US16208989

申请日：2018-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： JUN GYU LEE ,  REUM OH ,  KI HEUNG KIM ,  MOON HEE OH

IPC: G06F3/06 ,  G06F13/16 ,  G06F12/02 ,  G11C7/10

Abstract: According to some embodiments, a high bandwidth memory device includes a base die and a plurality of memory dies stacked on the base die and electrically connected to the base die through a plurality of through substrate vias. The base die includes a plurality of first input buffers configured to receive channel clock signals, channel command/addresses, and channel data from a plurality of first bumps connected to the outside of the base die, a plurality of second input buffers configured to receive test clock signals, test command/addresses, and test data from a plurality of second bumps connected to the outside of the base die, a monitoring unit, a plurality of first output buffers connected to the monitoring unit and configured to output monitored data from the monitoring unit to the plurality of second bumps, and a plurality of paths from the plurality of first input buffers to the monitoring unit. The plurality of second bumps are connected to receive test clock signals, test command/addresses, and test data from the outside of the base die during a first operation mode, and to receive monitored data from the plurality of first output buffers during a second operation mode.

公开(公告)号：US20130336079A1

公开(公告)日：2013-12-19

申请号：US13803520

申请日：2013-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KI HEUNG KIM ,  In Chul Jeong

IPC: G11C11/402

CPC classification number: G11C11/402 ,  G11C11/40618

Abstract: A memory refresh method includes selecting at least one bank from among N banks of a memory device, and activating K word lines from among a plurality of word lines included in the at least one bank during one of L refresh cycles of a refresh period. Each of the N banks comprises M word lines, N, K and M are each a natural number greater than or equal to two, L is a natural number less than or equal to M, and K is equal to M*N/L.

Abstract translation: 存储器刷新方法包括从存储器件的N个存储体中选择至少一个存储区，以及在刷新周期的L个刷新周期之一中激活包括在所述至少一个存储体中的多个字线中的K个字线。 每个N个组包括M个字线，N，K和M各自是大于或等于2的自然数，L是小于或等于M的自然数，K等于M * N / L。

公开(公告)号：US20220244882A1

公开(公告)日：2022-08-04

申请号：US17728107

申请日：2022-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： JUN GYU LEE ,  REUM OH ,  KI HEUNG KIM ,  MOON HEE OH

IPC: G06F3/06 ,  G11C7/10 ,  G06F12/02 ,  G06F13/16

Abstract: According to some embodiments, for a memory device including a base die and a stack of memory dies including a plurality of memory dies stacked on the base die, the base die including a plurality of first input/output (i/o) terminals that are command/address and data terminals and a plurality of second i/o terminals that are direct access terminals, a method includes receiving at the plurality of first i/o terminals a command/address, a clock signal, and data; first transmitting the command/address, clock signal, and data received by the plurality of first i/o terminals from the base die to the stack of memory dies; and second transmitting at least part of one or more of the command/address, clock signal, and data received by a set of the plurality of first i/o terminals through a circuit of the base die to the plurality of second i/o terminals.

公开(公告)号：US20210165597A1

公开(公告)日：2021-06-03

申请号：US17173779

申请日：2021-02-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： JUN GYU LEE ,  REUM OH ,  KI HEUNG KIM ,  MOON HEE OH

IPC: G06F3/06 ,  G11C7/10 ,  G06F12/02 ,  G06F13/16

Abstract: According to some embodiments, a high bandwidth memory device includes a base die and a plurality of memory dies stacked on the base die and electrically connected to the base die through a plurality of through substrate vias. The base die includes a plurality of first input buffers configured to receive channel clock signals, channel command/addresses, and channel data from a plurality of first bumps connected to the outside of the base die, a plurality of second input buffers configured to receive test clock signals, test command/addresses, and test data from a plurality of second bumps connected to the outside of the base die, a monitoring unit, a plurality of first output buffers connected to the monitoring unit and configured to output monitored data from the monitoring unit to the plurality of second bumps, and a plurality of paths from the plurality of first input buffers to the monitoring unit. The plurality of second bumps are connected to receive test clock signals, test command/addresses, and test data from the outside of the base die during a first operation mode, and to receive monitored data from the plurality of first output buffers during a second operation mode.

公开(公告)号：US20210165596A1

公开(公告)日：2021-06-03

申请号：US17173754

申请日：2021-02-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： JUN GYU LEE ,  REUM OH ,  KI HEUNG KIM ,  MOON HEE OH

IPC: G06F3/06 ,  G11C7/10 ,  G06F12/02 ,  G06F13/16

Abstract: According to some embodiments, a high bandwidth memory device includes a base die and a plurality of memory dies stacked on the base die and electrically connected to the base die through a plurality of through substrate vias. The base die includes a plurality of first input buffers configured to receive channel clock signals, channel command/addresses, and channel data from a plurality of first bumps connected to the outside of the base die, a plurality of second input buffers configured to receive test clock signals, test command/addresses, and test data from a plurality of second bumps connected to the outside of the base die, a monitoring unit, a plurality of first output buffers connected to the monitoring unit and configured to output monitored data from the monitoring unit to the plurality of second bumps, and a plurality of paths from the plurality of first input buffers to the monitoring unit. The plurality of second bumps are connected to receive test clock signals, test command/addresses, and test data from the outside of the base die during a first operation mode, and to receive monitored data from the plurality of first output buffers during a second operation mode.