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公开(公告)号：US20170352392A1
公开(公告)日：2017-12-07
申请号：US15479971
申请日：2017-04-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： HAE-SUK LEE , REUM OH , JIN-SEONG PARK , SEUNG-HAN WOO
IPC: G11C7/22 , H03K19/21 , H03K3/356 , G11C5/06 , G11C5/02 , G11C7/12 , G11C7/10 , G11C7/06 , H04L7/033 , H01L25/065
CPC classification number: G11C7/222 , G11C5/02 , G11C5/025 , G11C5/06 , G11C5/063 , G11C7/065 , G11C7/10 , G11C7/1006 , G11C7/1069 , G11C7/1096 , G11C7/12 , H01L25/0657 , H01L2224/16225 , H01L2225/06544 , H03K3/356104 , H03K3/356156 , H03K19/21 , H04L7/033
Abstract: A stacked semiconductor device includes a plurality of semiconductor dies stacked in a vertical direction, first and second signal paths, a transmission unit and a reception unit. The first and second signal paths electrically connect the plurality of semiconductor dies, where each of the first signal path and the second signal path includes at least one through-substrate via. The transmission unit generates a first driving signal and a second driving signal in synchronization with transitioning timing of a transmission signal to output the first driving signal to the first signal path and output the second driving signal to the second signal path. The reception unit receives a first attenuated signal corresponding to the first driving signal from the first signal path and receives a second attenuated signal corresponding to the second driving signal from the second signal path to generate a reception signal corresponding to the transmission signal.
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公开(公告)号：US20190198061A1
公开(公告)日：2019-06-27
申请号：US16293372
申请日：2019-03-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： REUM OH , JE-MIN RYU , PAVAN KUMAR KASIBHATLA
IPC: G11C5/02 , G06F12/0893 , G11C29/12 , G11C29/48 , G06F12/084 , G11C7/10
CPC classification number: G11C5/02 , G06F12/084 , G06F12/0893 , G11C5/025 , G11C7/1006 , G11C29/1201 , G11C29/48 , G11C2207/2245 , H01L25/18
Abstract: A memory device includes a memory cell array having a plurality of memory cell groups with a corresponding plurality of independent channels, and the device and an operating method thereof perform an internal data processing operation for the memory cell groups. The memory device includes an internal command generator configured to generate one or more internal commands in order to perform an internal data processing operation in response to a reception of a command, and an internal common bus for a common internal processing channel which is disposed to be shared by the plurality of memory cell groups and configured to form a transmission path of data between the plurality of memory cell groups when the internal data processing operation is performed.
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公开(公告)号：US20170358327A1
公开(公告)日：2017-12-14
申请号：US15607699
申请日：2017-05-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： REUM OH , JE-MIN RYU , PAVAN KUMAR KASIBHATLA
IPC: G11C5/02 , G06F12/0893 , G06F12/084 , G11C7/10 , H01L25/18
CPC classification number: G11C5/02 , G06F12/084 , G06F12/0893 , G11C5/025 , G11C7/1006 , G11C29/1201 , G11C29/48 , G11C2207/2245 , H01L25/18
Abstract: A memory device includes a memory cell array having a plurality of memory cell groups with a corresponding plurality of independent channels, and the device and an operating method thereof perform an internal data processing operation for the memory cell groups. The memory device includes an internal command generator configured to generate one or more internal commands in order to perform an internal data processing operation in response to a reception of a command, and an internal common bus for a common internal processing channel which is disposed to be shared by the plurality of memory cell groups and configured to form a transmission path of data between the plurality of memory cell groups when the internal data processing operation is performed.
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公开(公告)号：US20230064572A1
公开(公告)日：2023-03-02
申请号：US17742175
申请日：2022-05-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： DONGYEON PARK , YOUNGJAE PARK , HYUNGJIN KIM , REUM OH , JINYONG CHOI
IPC: G06F1/3225 , G06F1/3234 , G06F1/3296
Abstract: In a method of operating a memory device, a first command to allow the memory device to enter an idle mode is received. A reference time interval is adjusted based on process, voltage and temperature (PVT) variation associated with the memory device. The reference time interval is used to determine a start time point of a power control operation for reducing power consumption of the memory device. A first time interval during which the idle mode is maintained is internally measured based on the first command. The power control operation is performed in response to the first time interval being longer than the reference time interval.
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公开(公告)号：US20190278511A1
公开(公告)日：2019-09-12
申请号：US16208989
申请日：2018-12-04
Applicant: Samsung Electronics Co., Ltd.
Inventor： JUN GYU LEE , REUM OH , KI HEUNG KIM , MOON HEE OH
Abstract: According to some embodiments, a high bandwidth memory device includes a base die and a plurality of memory dies stacked on the base die and electrically connected to the base die through a plurality of through substrate vias. The base die includes a plurality of first input buffers configured to receive channel clock signals, channel command/addresses, and channel data from a plurality of first bumps connected to the outside of the base die, a plurality of second input buffers configured to receive test clock signals, test command/addresses, and test data from a plurality of second bumps connected to the outside of the base die, a monitoring unit, a plurality of first output buffers connected to the monitoring unit and configured to output monitored data from the monitoring unit to the plurality of second bumps, and a plurality of paths from the plurality of first input buffers to the monitoring unit. The plurality of second bumps are connected to receive test clock signals, test command/addresses, and test data from the outside of the base die during a first operation mode, and to receive monitored data from the plurality of first output buffers during a second operation mode.
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Patent Agency Ranking
公开(公告)号：US20250169067A1
公开(公告)日：2025-05-22
申请号：US19028305
申请日：2025-01-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： JAESAN KIM , SEUNGHAN WOO , HAESUK LEE , YOUNGCHEON KWON , REUM OH
IPC: H10B12/00 , H01L23/48 , H01L23/528 , H10D1/43 , H10D1/66
Abstract: A semiconductor device includes a semiconductor structure including a semiconductor substrate having an active zone with a channel; a through silicon via (TSV) structure including a power TSV configured to transmit power and a signal TSV configured to transmit a signal; and a keep-out zone located a predetermined distance away from the TSV structure and bounded by the active zone. The TSV structure penetrates the semiconductor substrate. The keep-out zone includes a first element area a first distance away from the power TSV, and a second element area a second distance away from the signal TSV.
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公开(公告)号：US20180358055A1
公开(公告)日：2018-12-13
申请号：US16106492
申请日：2018-08-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： REUM OH , JE-MIN RYU , PAVAN KUMAR KASIBHATLA
IPC: G11C5/02 , G11C29/12 , G06F12/0893 , G11C7/10 , G11C29/48 , G06F12/084 , H01L25/18
CPC classification number: G11C5/02 , G06F12/084 , G06F12/0893 , G11C5/025 , G11C7/1006 , G11C29/1201 , G11C29/48 , G11C2207/2245 , H01L25/18
Abstract: A memory device includes a memory cell array having a plurality of memory cell groups with a corresponding plurality of independent channels, and the device and an operating method thereof perform an internal data processing operation for the memory cell groups. The memory device includes an internal command generator configured to generate one or more internal commands in order to perform an internal data processing operation in response to a reception of a command, and an internal common bus for a common internal processing channel which is disposed to be shared by the plurality of memory cell groups and configured to form a transmission path of data between the plurality of memory cell groups when the internal data processing operation is performed.
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公开(公告)号：US20220244882A1
公开(公告)日：2022-08-04
申请号：US17728107
申请日：2022-04-25
Applicant: Samsung Electronics Co., Ltd.
Inventor： JUN GYU LEE , REUM OH , KI HEUNG KIM , MOON HEE OH
Abstract: According to some embodiments, for a memory device including a base die and a stack of memory dies including a plurality of memory dies stacked on the base die, the base die including a plurality of first input/output (i/o) terminals that are command/address and data terminals and a plurality of second i/o terminals that are direct access terminals, a method includes receiving at the plurality of first i/o terminals a command/address, a clock signal, and data; first transmitting the command/address, clock signal, and data received by the plurality of first i/o terminals from the base die to the stack of memory dies; and second transmitting at least part of one or more of the command/address, clock signal, and data received by a set of the plurality of first i/o terminals through a circuit of the base die to the plurality of second i/o terminals.
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公开(公告)号：US20210165597A1
公开(公告)日：2021-06-03
申请号：US17173779
申请日：2021-02-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： JUN GYU LEE , REUM OH , KI HEUNG KIM , MOON HEE OH
Abstract: According to some embodiments, a high bandwidth memory device includes a base die and a plurality of memory dies stacked on the base die and electrically connected to the base die through a plurality of through substrate vias. The base die includes a plurality of first input buffers configured to receive channel clock signals, channel command/addresses, and channel data from a plurality of first bumps connected to the outside of the base die, a plurality of second input buffers configured to receive test clock signals, test command/addresses, and test data from a plurality of second bumps connected to the outside of the base die, a monitoring unit, a plurality of first output buffers connected to the monitoring unit and configured to output monitored data from the monitoring unit to the plurality of second bumps, and a plurality of paths from the plurality of first input buffers to the monitoring unit. The plurality of second bumps are connected to receive test clock signals, test command/addresses, and test data from the outside of the base die during a first operation mode, and to receive monitored data from the plurality of first output buffers during a second operation mode.
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公开(公告)号：US20210165596A1
公开(公告)日：2021-06-03
申请号：US17173754
申请日：2021-02-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： JUN GYU LEE , REUM OH , KI HEUNG KIM , MOON HEE OH
Abstract: According to some embodiments, a high bandwidth memory device includes a base die and a plurality of memory dies stacked on the base die and electrically connected to the base die through a plurality of through substrate vias. The base die includes a plurality of first input buffers configured to receive channel clock signals, channel command/addresses, and channel data from a plurality of first bumps connected to the outside of the base die, a plurality of second input buffers configured to receive test clock signals, test command/addresses, and test data from a plurality of second bumps connected to the outside of the base die, a monitoring unit, a plurality of first output buffers connected to the monitoring unit and configured to output monitored data from the monitoring unit to the plurality of second bumps, and a plurality of paths from the plurality of first input buffers to the monitoring unit. The plurality of second bumps are connected to receive test clock signals, test command/addresses, and test data from the outside of the base die during a first operation mode, and to receive monitored data from the plurality of first output buffers during a second operation mode.
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