公开(公告)号：US20230343746A1

公开(公告)日：2023-10-26

申请号：US18128871

申请日：2023-03-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minkyeong Park ,  Sangsub Song ,  Kihong Jeong

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L25/0652 ,  H01L23/5386 ,  H01L24/08 ,  H01L24/09 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2924/182 ,  H10B80/00

Abstract: A semiconductor package includes a substrate, a first chip structure disposed on the substrate, a second chip structure disposed on the substrate, at least one controller disposed between the first chip structure and the second chip structure, the at least one controller including edge pads disposed on edges opposing each other in a first direction, and center pads disposed between the edge pads, and bonding wire structures. The substrate includes first bonding pads arranged in a second direction, perpendicular to the first direction, and second bonding pads arranged in the second direction in at least one of a space between the first bonding pads and the first chip structure and a space between the first bonding pads and the second chip structure. The bonding wire structures include a first bonding wire structure connecting the edge pads to the first bonding pads, and a second bonding wire structure connecting the center pads to the second bonding pads.

公开(公告)号：US12237302B2

公开(公告)日：2025-02-25

申请号：US18101246

申请日：2023-01-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kihong Jeong ,  Sangsub Song

IPC: H01L25/065 ,  H01L25/18

Abstract: A semiconductor package includes a package substrate, a processor chip mounted on the package substrate, a first stack structure on the package substrate, the first stack structure including a number M of memory chips stacked on the processor chip, and a second stack structure on the package substrate and spaced apart from the processor chip, the second stack structure including a number N of memory chips stacked on the package substrate. A number Q of channels that electrically connect the memory chips of the second stack structure with the processor chip may be greater than a number P of channels that electrically connect the memory chips of the first stack structure with the processor chip, or the number N of memory chips included in the second stack structure may be greater than the number M of memory chips included in the first stack structure.

公开(公告)号：US11569200B2

公开(公告)日：2023-01-31

申请号：US17015346

申请日：2020-09-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kihong Jeong ,  Sangsub Song

IPC: H01L25/065 ,  H01L25/18

Abstract: A semiconductor package includes a package substrate, a processor chip mounted on the package substrate, a first stack structure on the package substrate, the first stack structure including a number M of memory chips stacked on the processor chip, and a second stack structure on the package substrate and spaced apart from the processor chip, the second stack structure including a number N of memory chips stacked on the package substrate. A number Q of channels that electrically connect the memory chips of the second stack structure with the processor chip may be greater than a number P of channels that electrically connect the memory chips of the first stack structure with the processor chip, or the number N of memory chips included in the second stack structure may be greater than the number M of memory chips included in the first stack structure.