公开(公告)号：US20230343746A1

公开(公告)日：2023-10-26

申请号：US18128871

申请日：2023-03-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minkyeong Park ,  Sangsub Song ,  Kihong Jeong

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L25/0652 ,  H01L23/5386 ,  H01L24/08 ,  H01L24/09 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2924/182 ,  H10B80/00

Abstract: A semiconductor package includes a substrate, a first chip structure disposed on the substrate, a second chip structure disposed on the substrate, at least one controller disposed between the first chip structure and the second chip structure, the at least one controller including edge pads disposed on edges opposing each other in a first direction, and center pads disposed between the edge pads, and bonding wire structures. The substrate includes first bonding pads arranged in a second direction, perpendicular to the first direction, and second bonding pads arranged in the second direction in at least one of a space between the first bonding pads and the first chip structure and a space between the first bonding pads and the second chip structure. The bonding wire structures include a first bonding wire structure connecting the edge pads to the first bonding pads, and a second bonding wire structure connecting the center pads to the second bonding pads.

公开(公告)号：US20230260889A1

公开(公告)日：2023-08-17

申请号：US18110472

申请日：2023-02-16

Applicant: SAMSUNG ELECTRONICS CO. LTD.

Inventor： Sangnam JEONG ,  Sangsub Song

IPC: H01L23/498 ,  H10B80/00 ,  H05K1/18

CPC classification number: H01L23/49838 ,  H01L23/49816 ,  H05K1/181 ,  H10B80/00 ,  H01L24/16

Abstract: A semiconductor package includes: a package substrate including a plurality of insulating layers and a plurality of metal pattern layers respectively disposed on the plurality of insulating layers, wherein each of the plurality of metal pattern layers has an interconnection layer; at least one semiconductor chip disposed on an upper surface of the package substrate, and connected to the interconnection layer; contact pads disposed on a lower surface of the package substrate, and connected to the interconnection layer; and non-contact pads disposed on the lower surface of the package substrate, and insulated from the interconnection layer, wherein a lowermost metal pattern layer among the plurality of metal pattern layers has a first open region at least partially overlapping at least one non-contact pad among the non-contact pads, in a direction perpendicular to the upper surface of the package substrate.

公开(公告)号：US12237302B2

公开(公告)日：2025-02-25

申请号：US18101246

申请日：2023-01-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kihong Jeong ,  Sangsub Song

IPC: H01L25/065 ,  H01L25/18

Abstract: A semiconductor package includes a package substrate, a processor chip mounted on the package substrate, a first stack structure on the package substrate, the first stack structure including a number M of memory chips stacked on the processor chip, and a second stack structure on the package substrate and spaced apart from the processor chip, the second stack structure including a number N of memory chips stacked on the package substrate. A number Q of channels that electrically connect the memory chips of the second stack structure with the processor chip may be greater than a number P of channels that electrically connect the memory chips of the first stack structure with the processor chip, or the number N of memory chips included in the second stack structure may be greater than the number M of memory chips included in the first stack structure.

公开(公告)号：US20240243096A1

公开(公告)日：2024-07-18

申请号：US18413115

申请日：2024-01-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Moonyong Jang ,  Sangsub Song ,  Keunyoung Lee

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/0652 ,  H01L23/49816 ,  H01L24/48 ,  H01L24/32 ,  H01L24/33 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49052 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/06562

Abstract: Embodiments of the present disclosure include a semiconductor package comprising a first substrate including a plurality of wires stacked in a plurality of layers in a vertical direction, a plurality of chip stack structures spaced apart from each other on the first substrate and arranged in a first direction, a processor chip disposed on the first substrate, and a chip-to-chip wire connecting a chip stack structure that is disposed closest to the processor chip among the plurality of chip stack structures, wherein each of the plurality of chip stack structures includes a plurality of semiconductor chips offset-stacked in the first direction and a plurality of wires connecting the plurality of semiconductor chips to one another.

公开(公告)号：US11569200B2

公开(公告)日：2023-01-31

申请号：US17015346

申请日：2020-09-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kihong Jeong ,  Sangsub Song

IPC: H01L25/065 ,  H01L25/18

Abstract: A semiconductor package includes a package substrate, a processor chip mounted on the package substrate, a first stack structure on the package substrate, the first stack structure including a number M of memory chips stacked on the processor chip, and a second stack structure on the package substrate and spaced apart from the processor chip, the second stack structure including a number N of memory chips stacked on the package substrate. A number Q of channels that electrically connect the memory chips of the second stack structure with the processor chip may be greater than a number P of channels that electrically connect the memory chips of the first stack structure with the processor chip, or the number N of memory chips included in the second stack structure may be greater than the number M of memory chips included in the first stack structure.

公开(公告)号：US11500796B2

公开(公告)日：2022-11-15

申请号：US17172420

申请日：2021-02-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangsub Song

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/38

Abstract: An interface device between a plurality of memory devices and a memory controller includes processing circuitry configured to provide a plurality of controller channels for communicating with the memory controller, to provide a plurality of memory channels for communicating with the plurality of memory devices, and to connect each of the plurality of controller channels to at least one of the plurality of memory channels in a first mode and disconnect the plurality of controller channels from the plurality of memory channels in a second mode.