公开(公告)号：US20230223327A1

公开(公告)日：2023-07-13

申请号：US18076137

申请日：2022-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minkyeong Park ,  Yongsung Park

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/49838 ,  H01L24/73 ,  H01L24/48 ,  H01L24/32 ,  H01L24/33 ,  H01L24/49 ,  H01L25/0657 ,  H01L24/16 ,  H01L23/49816 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06562 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/73253 ,  H01L2225/06568 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/4903 ,  H01L2224/49052 ,  H01L2224/3201 ,  H01L2224/3303 ,  H01L23/49822

Abstract: A package base substrate includes a base layer; a plurality of lower surface connection pads disposed on a lower surface of the base layer; a plurality of lower surface wiring patterns disposed on a lower surface of the base layer and respectively connected to a set of lower surface connection pads of the plurality of lower surface connection pads; and a lower surface solder resist layer covering a portion of each of the plurality of lower surface connection pads and the plurality of lower surface wiring patterns on a lower surface of the base layer, wherein each of at least some of the lower surface connection pads of the set of lower surface connection pads has a teardrop shape in a plan view, and includes a ball land portion having a planar circular shape, including a terminal contact portion exposed without being covered by the lower surface solder resist layer, and an edge portion surrounding the terminal contact portion and covered by the lower surface solder resist layer; and a connection reinforcement portion between the ball land portion and the lower surface wiring pattern, including an extension line portion having a width that is the same as a line width of the lower surface wiring pattern and extending from the ball land portion to the lower surface wiring pattern, and a corner reinforcement portion filling a corner between the ball land portion and the extension line portion, and wherein an extension length of the extension line portion has a value greater than a radius of the terminal contact portion.

公开(公告)号：US20190237432A1

公开(公告)日：2019-08-01

申请号：US16377352

申请日：2019-04-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chul Park ,  Seonggwan Lee ,  Minkyeong Park

IPC: H01L25/065 ,  H01L25/04 ,  H01L25/07 ,  H01L25/11 ,  H01L25/075

Abstract: A semiconductor package includes a substrate including a signal pattern on an upper surface thereof, a chip stack on the substrate, and a first semiconductor chip and one or more spacers between the substrate and the chip stack. The chip stack includes one or more second semiconductor chips stacked on the substrate. The one or more spacers and the first semiconductor chip are adjacent to respective corners of a lowermost second semiconductor chip, in plan view. The one or more spacers have the same planar shape as the first semiconductor chip.

公开(公告)号：US20230343746A1

公开(公告)日：2023-10-26

申请号：US18128871

申请日：2023-03-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minkyeong Park ,  Sangsub Song ,  Kihong Jeong

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L25/0652 ,  H01L23/5386 ,  H01L24/08 ,  H01L24/09 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2924/182 ,  H10B80/00

Abstract: A semiconductor package includes a substrate, a first chip structure disposed on the substrate, a second chip structure disposed on the substrate, at least one controller disposed between the first chip structure and the second chip structure, the at least one controller including edge pads disposed on edges opposing each other in a first direction, and center pads disposed between the edge pads, and bonding wire structures. The substrate includes first bonding pads arranged in a second direction, perpendicular to the first direction, and second bonding pads arranged in the second direction in at least one of a space between the first bonding pads and the first chip structure and a space between the first bonding pads and the second chip structure. The bonding wire structures include a first bonding wire structure connecting the edge pads to the first bonding pads, and a second bonding wire structure connecting the center pads to the second bonding pads.

公开(公告)号：US11508687B2

公开(公告)日：2022-11-22

申请号：US16950211

申请日：2020-11-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minkyeong Park ,  Do-Hyun Kim

IPC: H01L23/00 ,  H01L25/18 ,  H01L25/00 ,  H01L23/538 ,  H01L21/56

Abstract: A semiconductor package may include a substrate including a first coupling terminal and a second coupling terminal, a first chip disposed on the substrate, the first chip including a first pad and a second pad, and a connection structure connecting the first coupling terminal to the first pad. A portion of the connection structure may be in contact with a first side surface of the first chip. The connection structure may include a connection conductor electrically connecting the first pad to the first coupling terminal.

公开(公告)号：US12237304B2

公开(公告)日：2025-02-25

申请号：US17665810

申请日：2022-02-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minkyeong Park ,  Do-Hyun Kim ,  Jaekyu Sung

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498

Abstract: A semiconductor package including a package substrate including first and second bonding pads, third bonding pads spaced apart from the first bonding pads, and fourth bonding pads spaced apart from the second bonding pads; a first chip stack including first chips stacked on the package substrate, each first chip including first signal pads and first power/ground pads alternately arranged; a second chip stack including second chips stacked on the first chip stack, each second chip including second signal pads and second power/ground pads alternately arranged; first lower wires that connect the first signal pads to the first bonding pads; second lower wires that connect the first power/ground pads to the second bonding pads; first upper wires that connect the second signal pads of the second chips to the third bonding pads; and second upper wires that connect the second power/ground pads of the second chips to the fourth bonding pads.

公开(公告)号：US10741526B2

公开(公告)日：2020-08-11

申请号：US16377352

申请日：2019-04-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chul Park ,  Seonggwan Lee ,  Minkyeong Park

IPC: H01L25/065 ,  H01L25/04 ,  H01L25/07 ,  H01L25/11 ,  H01L25/075

Abstract: A semiconductor package includes a substrate including a signal pattern on an upper surface thereof, a chip stack on the substrate, and a first semiconductor chip and one or more spacers between the substrate and the chip stack. The chip stack includes one or more second semiconductor chips stacked on the substrate. The one or more spacers and the first semiconductor chip are adjacent to respective corners of a lowermost second semiconductor chip, in plan view. The one or more spacers have the same planar shape as the first semiconductor chip.