公开(公告)号：US20190079760A1

公开(公告)日：2019-03-14

申请号：US16189642

申请日：2018-11-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-soo Sohn ,  Sei-jin KIM ,  Kwang-il PARK ,  Tae-young KIM ,  Chul-woo PARK

IPC: G06F9/30 ,  G06F12/00 ,  G06F15/78

Abstract: A memory device performing an internal copy operation is provided. The memory device may receive a source address, a destination address, and page size information together with an internal copy command, compares the source address with the destination address, and performs an internal copy operation. The internal copy operation may be an internal block copy operation, an inter-bank copy operation, or an internal bank copy operation. The internal copy operation may be performed with respect to one-page data, half-page data, or quarter-page data, based on the page size information. The memory device may output as a flag signal a copy-done signal indicating that the internal copy operation has been completed.

公开(公告)号：US20180358109A1

公开(公告)日：2018-12-13

申请号：US15850152

申请日：2017-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye-jung Kwon ,  Kwang-il PARK ,  Seung-jun BAE ,  Eun-sung SEO

IPC: G11C29/50 ,  G11C5/14

CPC classification number: G11C29/50 ,  G11C5/145 ,  G11C5/147 ,  G11C7/1063 ,  G11C11/4074 ,  G11C29/02 ,  G11C29/04 ,  G11C29/12005 ,  G11C29/50004 ,  G11C29/50012 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/5004 ,  G11C2029/5006

Abstract: Memory devices and methods of operating the same are provided. The memory device including at least one internal circuit including a memory cell array and a peripheral circuit configured to drive the memory cell array, a monitor logic configured to monitor a current flowing into the at least one internal circuit and output a monitoring result, a detect logic configured to detect whether a leakage current flows in the at least one internal circuit based on the monitoring result, and output detected information regarding the leakage current, and diagnosis logic configured to diagnose an error in the at least one internal circuit based on the detected information.

公开(公告)号：US20130054904A1

公开(公告)日：2013-02-28

申请号：US13660031

申请日：2012-10-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-hyup KWAK ,  Kwang-il PARK ,  Seung-jun BAE

IPC: G06F12/00

CPC classification number: G11C7/1078 ,  G11C7/1006 ,  G11C11/4096

Abstract: A data mask system includes a processor providing control signals including a command signal, an address signal, and a data signal, a data mask processor receiving the control signals and providing either write data or masked data in response to the control signals, and generating data mask information and a data mask selection signal from at least one of the control signals, and a data mask register unit receiving the data mask selection signal, storing the data mask information, selecting a subset of the stored data mask information in response to the data mask selection signal, and returning selected data mask information to the data mask processor. The data mask processor receives the selected data mask information from the data mask register unit and provides the masked data as a result of performing a data mask operation on the data signal according to the selected data mask information.

Abstract translation: 数据掩模系统包括提供包括命令信号，地址信号和数据信号的控制信号的处理器，接收控制信号的数据掩码处理器，并响应于控制信号提供写数据或屏蔽数据，并产生数据 来自至少一个控制信号的掩模信息和数据掩模选择信号，以及接收数据掩码选择信号的数据掩码寄存器单元，存储数据掩码信息，响应于数据选择存储的数据掩码信息的子集 掩模选择信号，并将选择的数据掩码信息返回到数据掩码处理器。 数据掩模处理器从数据掩码寄存器单元接收所选择的数据掩码信息，并根据所选择的数据掩码信息提供作为数据信号的数据掩码操作的结果的掩蔽数据。

公开(公告)号：US20200257840A1

公开(公告)日：2020-08-13

申请号：US16788924

申请日：2020-02-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： In HUH ,  Jeong-hoon KO ,  Hyo-jin CHOI ,  Seung-ju KIM ,  Chang-wook JEONG ,  Joon-wan CHAI ,  Kwang-il PARK ,  Youn-sik PARK ,  Hyun-sun PARK ,  Young-min OH ,  Jun-haeng LEE ,  Tae-ho LEE

IPC: G06F30/33 ,  G06N3/08

Abstract: A device for verifying a circuit design including a first circuit block and a second circuit block includes a verification vector generator and a design verifier. The verification vector generator determines a first verification vector by performing reinforcement learning through neural network computation based on a coverage corresponding to a first test vector, the coverage being determined based on a state transition of the first circuit block generated by inputting the first test vector to the first circuit block. The design verifier performs design verification for the first circuit block by using the first verification vector.

公开(公告)号：US20140189370A1

公开(公告)日：2014-07-03

申请号：US14143574

申请日：2013-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyoung-Suk JANG ,  Kwang-il PARK ,  Hee-Chang CHO

IPC: G06F21/60

CPC classification number: G06F21/79

Abstract: A memory device includes an input/output (I/O) interface, a secure logic for receiving a storage verifying command including an expected value of secure data via the I/O interface, an I/O logic for receiving an input request for inputting user data into the memory device and/or an output request for outputting user data therefrom and perform one of the input request and/or the output request, and a memory unit including a secure area, accessible by the secure logic, for storing the secure data and a normal area, accessible by the I/O logic, for storing the user data. The secure logic reads the secure data from the secure area in response to the input of the storage verifying command and outputs a storage verifying result to the external device, without outputting the secure data to the external device, according to whether the secure data expected value is identical with the secure data.

Abstract translation: 存储装置包括输入/​​输出（I / O）接口，用于经由I / O接口接收包括安全数据期望值的存储验证命令的安全逻辑，用于接收输入请求的I / O逻辑 将用户数据存入存储器装置和/或从其输出用户数据的输出请求和执行输入请求和/或输出请求之一的输出请求，以及包括可由安全逻辑访问的安全区域的存储单元，用于存储安全 数据和正常区域，可由I / O逻辑访问，用于存储用户数据。 响应于存储验证命令的输入，安全逻辑从安全区域读取安全数据，并且根据安全数据期望值是否将安全数据输出到外部设备，并将存储验证结果输出到外部设备 与安全数据相同。