公开(公告)号：US20170365327A1

公开(公告)日：2017-12-21

申请号：US15611169

申请日：2017-06-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chankyung KIM ,  Sungchul PARK ,  Soo-Ho CHA ,  Seongil O ,  Kwangchol CHOE

IPC: G11C11/4091 ,  G11C11/4076 ,  G11C11/408

CPC classification number: G11C11/4091 ,  G11C5/025 ,  G11C5/04 ,  G11C8/12 ,  G11C11/4087 ,  G11C11/4093 ,  G11C11/4097 ,  G11C2207/107

Abstract: Memory devices may include a memory cell connected to a word line and a bit line, a first bit line sense amplifier connected to the memory cell through the bit line and configured to amplify a signal of the bit line, and a second bit line sense amplifier disposed adjacent to the first bit line sense amplifier and not connected to the bit line. The second bit line sense amplifier may be selected by an address received from a processor, and data may be stored in the second bit line sense amplifier or the data is output from the second bit line sense amplifier according to a command received from the processor. In some aspects described herein, the memory device may include a buffer memory that operates at high speed, thereby increasing performance of a memory module.