公开(公告)号：US20210357130A1

公开(公告)日：2021-11-18

申请号：US17389834

申请日：2021-07-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngjin CHO ,  Sungyong SEO ,  Sun-Young LIM ,  Uksong KANG ,  Chankyung KIM ,  Duckhyun CHANG ,  JinHyeok CHOI

IPC: G06F3/06 ,  G11C16/26 ,  G11C16/10 ,  G06F12/0868 ,  G06F12/0893 ,  G11C11/00 ,  G06F13/16

Abstract: A nonvolatile memory device includes a nonvolatile memory, a volatile memory being a cache memory of the nonvolatile memory, and a first controller configured to control the nonvolatile memory. The nonvolatile memory device further includes a second controller configured to receive a device write command and an address, and transmit, to the volatile memory through a first bus, a first read command and the address and a first write command and the address sequentially, and transmit a second write command and the address to the first controller through a second bus, in response to the reception of the device write command and the address.

公开(公告)号：US20170153826A1

公开(公告)日：2017-06-01

申请号：US15366137

申请日：2016-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngjin CHO ,  Sungyong SEO ,  Sun-Young LIM ,  Uksong KANG ,  Chankyung KIM ,  Duckhyun CHANG ,  JinHyeok CHOI

IPC: G06F3/06 ,  G06F12/0893 ,  G11C16/10 ,  G06F12/0868 ,  G11C14/00 ,  G11C16/26

CPC classification number: G06F3/0611 ,  G06F3/0656 ,  G06F3/0679 ,  G06F12/0868 ,  G06F12/0893 ,  G06F13/16 ,  G06F2212/1021 ,  G06F2212/1024 ,  G06F2212/205 ,  G06F2212/214 ,  G06F2212/3042 ,  G06F2212/305 ,  G06F2212/313 ,  G06F2212/7203 ,  G11C11/005 ,  G11C16/10 ,  G11C16/26 ,  G11C2207/2245

Abstract: A nonvolatile memory device includes a nonvolatile memory, a volatile memory being a cache memory of the nonvolatile memory, and a first controller configured to control the nonvolatile memory. The nonvolatile memory device further includes a second controller configured to receive a device write command and an address, and transmit, to the volatile memory through a first bus, a first read command and the address and a first write command and the address sequentially, and transmit a second write command and the address to the first controller through a second bus, in response to the reception of the device write command and the address.

公开(公告)号：US20220084591A1

公开(公告)日：2022-03-17

申请号：US17328248

申请日：2021-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chankyung KIM

IPC: G11C13/00

Abstract: A resistive memory device includes a resistive cell connected between a first bit line and a first source line, a reference cell including a reference resistor and connected between a second bit line and a second source line, and a write driver connected to the first bit line or the first source line, connected to the second bit line or the second source line. The write driver includes a comparator configured to compare previous data written in the resistive cell with the target data by comparing a voltage of the first source line with a voltage of the second source line or comparing a voltage of the first bit line with a voltage of the second bit line, and determine whether the target data is written in the resistive cell after comparing the previous data with the target data.

公开(公告)号：US20200035281A1

公开(公告)日：2020-01-30

申请号：US16401236

申请日：2019-05-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chankyung KIM ,  Taehyun KIM ,  Seongui SEO ,  Sangjung JEON

IPC: G11C11/16

Abstract: A memory device including: a memory cell array including a memory cell, the memory cell configured to store first data based on a first write current; a write driver configured to output the first write current based on a control value; and a current controller including a replica memory cell, the current controller configured to generate the control value based on a state of second data which is stored in the replica memory cell, wherein an intensity of the first write current is adjusted based on the control value.

公开(公告)号：US20190252005A1

公开(公告)日：2019-08-15

申请号：US16129948

申请日：2018-09-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chankyung KIM

IPC: G11C5/06 ,  G11C5/02 ,  G11C8/14 ,  G11C8/18

Abstract: A memory device includes a memory cell array that a plurality of memory cells, an edge buffer circuit that is placed in a first region adjacent to one side of the memory cell array and receives an external signal from the outside through a pad, and a middle buffer circuit that is placed in a second region adjacent to an opposite side of the memory cell array and receives a differential small-swing signal corresponding to the external signal from the edge buffer circuit through first and second signal lines above the memory cell array. The edge buffer circuit drives the first and second signal lines based on the external signal such that the differential small-swing signal is transmitted to the middle buffer circuit.

公开(公告)号：US20170365327A1

公开(公告)日：2017-12-21

申请号：US15611169

申请日：2017-06-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chankyung KIM ,  Sungchul PARK ,  Soo-Ho CHA ,  Seongil O ,  Kwangchol CHOE

IPC: G11C11/4091 ,  G11C11/4076 ,  G11C11/408

CPC classification number: G11C11/4091 ,  G11C5/025 ,  G11C5/04 ,  G11C8/12 ,  G11C11/4087 ,  G11C11/4093 ,  G11C11/4097 ,  G11C2207/107

Abstract: Memory devices may include a memory cell connected to a word line and a bit line, a first bit line sense amplifier connected to the memory cell through the bit line and configured to amplify a signal of the bit line, and a second bit line sense amplifier disposed adjacent to the first bit line sense amplifier and not connected to the bit line. The second bit line sense amplifier may be selected by an address received from a processor, and data may be stored in the second bit line sense amplifier or the data is output from the second bit line sense amplifier according to a command received from the processor. In some aspects described herein, the memory device may include a buffer memory that operates at high speed, thereby increasing performance of a memory module.

公开(公告)号：US20170206028A1

公开(公告)日：2017-07-20

申请号：US15479795

申请日：2017-04-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seongil O ,  Chankyung KIM ,  JongpiI SON

IPC: G06F3/06 ,  G06F12/128

CPC classification number: G06F12/0846 ,  G06F11/1064 ,  G06F11/34 ,  G06F12/0246 ,  G06F12/0844 ,  G06F12/0864 ,  G06F12/0884 ,  G06F12/128 ,  G06F2201/885 ,  G06F2212/1032 ,  G06F2212/214 ,  G06F2212/313 ,  G06F2212/7201 ,  G11C5/04 ,  G11C7/1072 ,  G11C7/22 ,  G11C11/40607 ,  G11C11/4093 ,  G11C11/4096 ,  G11C16/0483 ,  G11C16/32 ,  G11C29/26 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411 ,  G11C2029/5002 ,  G11C2207/2245

Abstract: A method includes outputting, at a processor, a command and an address to the memory module, receiving match/unmatch bits indicating results of comparing a tag corresponding to the address with tags stored in the memory module, from the memory module, determining, at the processor, a cache hit/miss from the match/unmatch bits by using majority voting, and outputting, at the processor, the determined cache hit/miss to the memory module.