公开(公告)号：US20230395132A1

公开(公告)日：2023-12-07

申请号：US18180623

申请日：2023-03-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： JONGSUN PARK ,  Kyeongho Lee ,  Hyunjun Kim

IPC: G11C11/4093 ,  G11C11/408 ,  G11C11/4094 ,  G06F7/501

CPC classification number: G11C11/4093 ,  G11C11/4085 ,  G11C11/4094 ,  G06F7/501

Abstract: An SRAM cell includes a first pass gate transistor connected with a first word-line and a local bit-line, a first inverter that includes an output terminal connected with the first pass gate transistor and an input terminal, a second inverter that includes an input terminal connected with the first pass gate transistor and an output terminal, a second pass gate transistor connected with a second word line, the input terminal of the first inverter and the output terminal of the second inverter, and a complementary local bit-line, a first transistor connected with the second pass gate transistor, a local computing line, and a ground electrode, and a second transistor connected with a third word-line, the local computing line, and the ground electrode.