公开(公告)号：US20210320125A1

公开(公告)日：2021-10-14

申请号：US17162408

申请日：2021-01-29

申请人： Samsung Electronics Co., Ltd.

发明人： Jaehoon SHIN ,  Kangmin KIM ,  Kyeongjin PARK ,  Seungmin SONG ,  Joongshik SHIN ,  Geunwon LIM

IPC分类号： H01L27/11582 ,  H01L27/11573 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11556 ,  H01L23/522

摘要： A vertical memory device includes a gate electrode structure, a channel, an insulation pattern structure, an etch stop structure, and a through via. The gate electrode structure includes gate electrodes spaced apart from each other on a substrate in a first direction perpendicular to an upper surface of the substrate, and each of the gate electrodes extends in a second direction parallel to the upper surface of the substrate. The channel extends in the first direction through the gate electrode structure. The insulation pattern structure extends through the gate electrode structure. The etch stop structure extends through the gate electrode structure and surround at least a portion of a sidewall of the insulation pattern structure, and the etch stop structure includes a filling pattern and an etch stop pattern on a sidewall of the filling pattern. The through via extends in the first direction through the insulation pattern structure.