公开(公告)号：US20220399900A1

公开(公告)日：2022-12-15

申请号：US17837752

申请日：2022-06-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyeongjoon KO ,  Jaehyun PARK ,  Junhan BAE ,  Gyeongseok SONG ,  Jongjae RYU

IPC: H03M1/68 ,  H03M1/74

Abstract: A digital-to-analog converter includes a current cell array including a plurality of current cells, each current cell of the plurality of current cells being configured to generate a current of a same magnitude; a first pattern connecting first current cells, among the plurality of current cells, arranged along a diagonal line of the current cell array; a second pattern connecting second current cells, among the plurality of current cells, arranged along a first oblique line parallel to the diagonal line; and a third pattern connecting third current cells, among the plurality of current cells, arranged along a second oblique line parallel to the diagonal line, the third pattern being electrically connected to the second pattern, wherein the diagonal line is between the first oblique line and the second oblique line.

公开(公告)号：US20220400037A1

公开(公告)日：2022-12-15

申请号：US17834262

申请日：2022-06-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyeongjoon KO ,  Hanseok KIM ,  Jaehyun PARK ,  Junhan BAE ,  Gyeongseok SONG ,  Jongjae RYU

IPC: H04L25/03

Abstract: Provided is an equalizer including: an input amplifier configured to amplify and output an input signal; a first equalization circuit including a first sampling circuit, a first arithmetic circuit, and a second arithmetic circuit, the first sampling circuit being configured to generate and output 1-1 to 1-N feedback signals, wherein N is a natural number greater than or equal to 2; and a second equalization circuit including a second sampling circuit, a third arithmetic circuit, and a fourth arithmetic circuit, the second sampling circuit being configured to generate and output 2-1 to 2-M feedback signals, wherein M is a natural number greater than or equal to 2.

公开(公告)号：US20220400036A1

公开(公告)日：2022-12-15

申请号：US17835373

申请日：2022-06-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyeongjoon KO ,  Jaehyun PARK ,  Junhan BAE ,  Gyeongseok SONG ,  Jongjae RYU

IPC: H04L25/03 ,  H03K19/20 ,  H03K3/037

Abstract: Provided are a summing circuit and an equalizer including the summing circuit. The summing circuit includes: a reference signal generator generating a first reference signal and a second reference signal, based on a coefficient code; a first non-overlap clock buffer generating a first switching signal and a second switching signal by using the first reference signal; and a first current source receiving the first switching signal and the second switching signal generated by the first non-overlap clock buffer, generating a first output current by using a bias voltage, and outputting the first output current to an output line, wherein the first switching signal includes a switching signal and a complementary switching signal that is a complementary signal to the switching signal, and wherein a logic low period of the second switching signal is included in a logic high period of the complementary switching signal of the first switching signal.

公开(公告)号：US20250062888A1

公开(公告)日：2025-02-20

申请号：US18934842

申请日：2024-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunggeun KIM ,  Nakwon LEE ,  Jaehyun PARK ,  Kyeongjoon KO ,  Kangjik KIM ,  Seuk SON ,  Byunghyun LIM

IPC: H04L7/00

Abstract: A clock data recovery circuit includes an inphase-quadrature (I-Q) merged phase interpolator circuit configured to generate a first clock pair and a second clock pair from a plurality of reference clock signals, the plurality of reference clock signals having different phases, the first clock pair comprising an I clock signal and an inverted I clock signal, and the second clock pair comprising a Q clock signal and an inverted Q clock signal, a sampler circuit configured to sample input data based on the first clock pair and the second clock pair, and a control circuit configured to control phases of the first clock pair and the second clock pair, the controlling including providing a control signal to the I-Q merged phase interpolator circuit based on a sampling result of the sampler circuit, the I-Q merged phase interpolator circuit is configured to share analog inputs based on the control signal.

公开(公告)号：US20230114988A1

公开(公告)日：2023-04-13

申请号：US17957414

申请日：2022-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunggeun KIM ,  Nakwon LEE ,  Jaehyun PARK ,  Kyeongjoon KO ,  Kangjik KIM ,  Seuk SON ,  Byunghyun LIM

IPC: H04L7/00

Abstract: A clock data recovery circuit includes an inphase-quadrature (I-Q) merged phase interpolator circuit configured to generate a first clock pair and a second clock pair from a plurality of reference clock signals, the plurality of reference clock signals having different phases, the first clock pair comprising an I clock signal and an inverted I clock signal, and the second clock pair comprising a Q clock signal and an inverted Q clock signal, a sampler circuit configured to sample input data based on the first clock pair and the second clock pair, and a control circuit configured to control phases of the first clock pair and the second clock pair, the controlling including providing a control signal to the I-Q merged phase interpolator circuit based on a sampling result of the sampler circuit, the I-Q merged phase interpolator circuit is configured to share analog inputs based on the control signal.