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1.发明申请公开(公告)号：US20160315625A1
公开(公告)日：2016-10-27
申请号：US15179202
申请日：2016-06-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Junhan BAE , Kee-Won KWON , Kyungho KIM , Jung Hoon CHUN , Youngsoo SOHN , Seok KIM
CPC classification number: H03L7/0891 , H03D13/004 , H03L7/081 , H03L7/085 , H03L7/087 , H03L7/0995 , H03L7/104 , H03L7/107 , H03L7/1072
Abstract: A phase-rotating phase locked loop (PLL) may include first and second loops that share a loop filter and a voltage controlled oscillator in order to perform the operation of a phase-rotating PLL, the first and second loops configured to activate in response to an enable signal. The PLL may further include a phase frequency detection controller configured to provide the enable signal to the first and second loops in response to a transition of a coarse signal that may be applied as a digital code.
Abstract translation: 相位旋转锁相环（PLL）可以包括共享环路滤波器和压控振荡器的第一和第二回路，以便执行相位旋转PLL的操作，第一和第二回路被配置为响应于 一个使能信号。 PLL可以进一步包括相位频率检测控制器，其被配置为响应于作为数字代码应用的粗略信号的转变，向第一和第二环路提供使能信号。
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2.发明申请公开(公告)号：US20140333346A1
公开(公告)日：2014-11-13
申请号：US14272975
申请日：2014-05-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Junhan BAE , Kee-won KWON , Kyoungho KIM , Jung Hoon CHUN , Youngsoo SOHN , Seok KIM
IPC: H03L7/087
CPC classification number: H03L7/0891 , H03D13/004 , H03L7/081 , H03L7/085 , H03L7/087 , H03L7/0995 , H03L7/104 , H03L7/107 , H03L7/1072
Abstract: A phase-rotating phase locked loop (PLL) may include first and second loops that share a loop filter and a voltage controlled oscillator in order to perform the operation of a phase-rotating PLL, the first and second loops configured to activate in response to an enable signal. The PLL may further include a phase frequency detection controller configured to provide the enable signal to the first and second loops in response to a transition of a coarse signal that may be applied as a digital code.
Abstract translation: 相位旋转锁相环（PLL）可以包括共享环路滤波器和压控振荡器的第一和第二回路，以便执行相位旋转PLL的操作，第一和第二回路被配置为响应于 一个使能信号。 PLL可以进一步包括相位频率检测控制器，其被配置为响应于作为数字代码应用的粗略信号的转变，向第一和第二环路提供使能信号。
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公开(公告)号：US20240430988A1
公开(公告)日：2024-12-26
申请号：US18769871
申请日：2024-07-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Minkyung LEE , Soobin KWON , Kwangjoo KIM , Sungmin CHO , Minsu KANG , Junhan BAE , Hyunseok SHIN , Youngdeog KOH , Hoon WEE
Abstract: A humidifying apparatus can include a water tank, and a duct through which water vapor generated in the water tank flows, wherein the water tank includes a bottom plate generating heat, the bottom plate includes a first glass plate disposed within the water tank and a second glass plate disposed below the first glass plate and spaced apart from the first glass plate, and the first glass plate includes a heating layer coated on a lower surface of the first glass plate, and the second glass plate includes a low emissivity layer coated on an upper surface of the second glass plate to suppress heat generated in the heating layer from being transferred to the outside of the second glass plate.
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Patent Agency Ranking
公开(公告)号：US20220399900A1
公开(公告)日：2022-12-15
申请号：US17837752
申请日：2022-06-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyeongjoon KO , Jaehyun PARK , Junhan BAE , Gyeongseok SONG , Jongjae RYU
Abstract: A digital-to-analog converter includes a current cell array including a plurality of current cells, each current cell of the plurality of current cells being configured to generate a current of a same magnitude; a first pattern connecting first current cells, among the plurality of current cells, arranged along a diagonal line of the current cell array; a second pattern connecting second current cells, among the plurality of current cells, arranged along a first oblique line parallel to the diagonal line; and a third pattern connecting third current cells, among the plurality of current cells, arranged along a second oblique line parallel to the diagonal line, the third pattern being electrically connected to the second pattern, wherein the diagonal line is between the first oblique line and the second oblique line.
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公开(公告)号：US20230130236A1
公开(公告)日：2023-04-27
申请号：US17972869
申请日：2022-10-25
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hobin SONG , Yungeun NAM , Byeonggyu PARK , Jaehyun PARK , Hajung PARK , Junhan BAE
Abstract: A device includes a receiver analog front-end circuit including a path shared by an internal loopback current path and a calibration current path, wherein the receiver analog front-end circuit is configured to perform an internal test using the internal loopback current path while in a test mode, and equalize a first data signal while in a normal mode, the equalizing the first data signal including removing an offset from the first data signal using the calibration current path.
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公开(公告)号：US20220400037A1
公开(公告)日：2022-12-15
申请号：US17834262
申请日：2022-06-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyeongjoon KO , Hanseok KIM , Jaehyun PARK , Junhan BAE , Gyeongseok SONG , Jongjae RYU
IPC: H04L25/03
Abstract: Provided is an equalizer including: an input amplifier configured to amplify and output an input signal; a first equalization circuit including a first sampling circuit, a first arithmetic circuit, and a second arithmetic circuit, the first sampling circuit being configured to generate and output 1-1 to 1-N feedback signals, wherein N is a natural number greater than or equal to 2; and a second equalization circuit including a second sampling circuit, a third arithmetic circuit, and a fourth arithmetic circuit, the second sampling circuit being configured to generate and output 2-1 to 2-M feedback signals, wherein M is a natural number greater than or equal to 2.
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公开(公告)号：US20220400036A1
公开(公告)日：2022-12-15
申请号：US17835373
申请日：2022-06-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyeongjoon KO , Jaehyun PARK , Junhan BAE , Gyeongseok SONG , Jongjae RYU
Abstract: Provided are a summing circuit and an equalizer including the summing circuit. The summing circuit includes: a reference signal generator generating a first reference signal and a second reference signal, based on a coefficient code; a first non-overlap clock buffer generating a first switching signal and a second switching signal by using the first reference signal; and a first current source receiving the first switching signal and the second switching signal generated by the first non-overlap clock buffer, generating a first output current by using a bias voltage, and outputting the first output current to an output line, wherein the first switching signal includes a switching signal and a complementary switching signal that is a complementary signal to the switching signal, and wherein a logic low period of the second switching signal is included in a logic high period of the complementary switching signal of the first switching signal.
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公开(公告)号：US20220222063A1
公开(公告)日：2022-07-14
申请号：US17573849
申请日：2022-01-12
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sangun BANG , Dongjo KIM , Jaehyun BAE , Junhan BAE , Duseung OH , Sungeun LEE , Arom LEE
Abstract: A portable device and an operating method of the same are provided. The portable device includes a power line communication module performing power line communication with an external device, a memory module storing firmware data, and a controller controlling the power line communication module and the memory module, wherein the power line communication module sequentially provides an update initiation signal and firmware data to the external device, and provides an update end signal to the external device in response to a response signal transmitted by the external device.
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