公开(公告)号：US20230291412A1

公开(公告)日：2023-09-14

申请号：US17974703

申请日：2022-10-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoungjun Roh ,  Jaewoo Park ,  Myoungbo Kwak ,  Jejoong Woo ,  Junghwan Choi

IPC: H03M1/18 ,  H03M1/48 ,  H03M1/12

CPC classification number: H03M1/186 ,  H03M1/121 ,  H03M1/48

Abstract: An electronic device which may include an analog-to-digital converter circuit that converts a level of an input signal to digital input values in response to a clock signal, an oscillator that generates the clock signal, a first equalization circuit that generates digital output signals by equalizing the digital input values, a first phase detector circuit that detects phases of the digital output signals and generates digital phase values, a loop filter that generates a first digital output value based on the digital phase values, a second equalization circuit that generates digital intermediate values by equalizing the digital input values, and a second phase detector circuit that detects phases of the digital intermediate values and to generate a second digital output value. The oscillator may adjust a frequency of the clock signal based on the first digital output value and the second digital output value.

公开(公告)号：US12176912B2

公开(公告)日：2024-12-24

申请号：US17974703

申请日：2022-10-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoungjun Roh ,  Jaewoo Park ,  Myoungbo Kwak ,  Jejoong Woo ,  Junghwan Choi

IPC: H03M1/18 ,  H03M1/12 ,  H03M1/48 ,  H03M1/10

Abstract: An electronic device which may include an analog-to-digital converter circuit that converts a level of an input signal to digital input values in response to a clock signal, an oscillator that generates the clock signal, a first equalization circuit that generates digital output signals by equalizing the digital input values, a first phase detector circuit that detects phases of the digital output signals and generates digital phase values, a loop filter that generates a first digital output value based on the digital phase values, a second equalization circuit that generates digital intermediate values by equalizing the digital input values, and a second phase detector circuit that detects phases of the digital intermediate values and to generate a second digital output value. The oscillator may adjust a frequency of the clock signal based on the first digital output value and the second digital output value.