EFFICIENT POLYPHASE ARCHITECTURE FOR INTERPOLATOR AND DECIMATOR

    公开(公告)号:US20180115329A1

    公开(公告)日:2018-04-26

    申请号:US15402651

    申请日:2017-01-10

    IPC分类号: H04B1/00 H04B3/462

    摘要: Apparatuses (and methods of manufacturing same), systems, and methods concerning polyphase digital filters are described. In one aspect, an apparatus is provided, including at least one pair of subfilters, each having symmetric coefficients, and a lattice comprising two adders and feedlines corresponding to each of the at least one pair of subfilters, each having symmetric coefficients. In one aspect, the apparatus is a polyphase finite impulse response (FIR) digital filter, including an interpolator and a decimator, where each of the interpolator and the decimator have at least one pair of subfilters, each having symmetric coefficients, and a lattice comprising two adders and feedlines corresponding to each of the at least one pair of subfilters, each having symmetric coefficients.

    EFFICIENT POLYPHASE ARCHITECTURE FOR INTERPOLATOR AND DECIMATOR

    公开(公告)号:US20210211144A1

    公开(公告)日:2021-07-08

    申请号:US17155723

    申请日:2021-01-22

    IPC分类号: H04B1/00 H04B3/462

    摘要: Apparatuses (and methods of manufacturing same), systems, and methods concerning polyphase digital filters are described. In one aspect, an apparatus is provided, including at least one pair of subfilters, each having symmetric coefficients, and a lattice comprising two adders and feedlines corresponding to each of the at least one pair of subfilters, each having symmetric coefficients. In one aspect, the apparatus is a polyphase finite impulse response (FIR) digital filter, including an interpolator and a decimator, where each of the interpolator and the decimator have at least one pair of subfilters, each having symmetric coefficients, and a lattice comprising two adders and feedlines corresponding to each of the at least one pair of subfilters, each having symmetric coefficients.

    EFFICIENT POLYPHASE ARCHITECTURE FOR INTERPOLATOR AND DECIMATOR

    公开(公告)号:US20200052726A1

    公开(公告)日:2020-02-13

    申请号:US16656971

    申请日:2019-10-18

    IPC分类号: H04B1/00 H04B3/462

    摘要: Apparatuses (and methods of manufacturing same), systems, and methods concerning polyphase digital filters are described. In one aspect, an apparatus is provided, including at least one pair of subfilters, each having symmetric coefficients, and a lattice comprising two adders and feedlines corresponding to each of the at least one pair of subfilters, each having symmetric coefficients. In one aspect, the apparatus is a polyphase finite impulse response (FIR) digital filter, including an interpolator and a decimator, where each of the interpolator and the decimator have at least one pair of subfilters, each having symmetric coefficients, and a lattice comprising two adders and feedlines corresponding to each of the at least one pair of subfilters, each having symmetric coefficients.

    EFFICIENT POLYPHASE ARCHITECTURE FOR INTERPOLATOR AND DECIMATOR

    公开(公告)号:US20180254785A1

    公开(公告)日:2018-09-06

    申请号:US15974218

    申请日:2018-05-08

    IPC分类号: H04B1/00 H04B3/462

    摘要: Apparatuses (and methods of manufacturing same), systems, and methods concerning polyphase digital filters are described. In one aspect, an apparatus is provided, including at least one pair of subfilters, each having symmetric coefficients, and a lattice comprising two adders and feedlines corresponding to each of the at least one pair of subfilters, each having symmetric coefficients. In one aspect, the apparatus is a polyphase finite impulse response (FIR) digital filter, including an interpolator and a decimator, where each of the interpolator and the decimator have at least one pair of subfilters, each having symmetric coefficients, and a lattice comprising two adders and feedlines corresponding to each of the at least one pair of subfilters, each having symmetric coefficients.