利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

55 条记录 (耗时 0.023 秒)

    EFFICIENT POLYPHASE ARCHITECTURE FOR INTERPOLATOR AND DECIMATOR
    2.
    发明申请
    EFFICIENT POLYPHASE ARCHITECTURE FOR INTERPOLATOR AND DECIMATOR 有权

    公开(公告)号：US20180115329A1

    公开(公告)日：2018-04-26

    申请号：US15402651

    申请日：2017-01-10

    申请人： Samsung Electronics Co., Ltd.

    发明人： Liangbin LI ,  Pranav DAYAL ,  Jungwon LEE ,  Gennady FEYGIN

    IPC分类号： H04B1/00 ,  H04B3/462

    CPC分类号： H04B1/0042 ,  H04B1/0046 ,  H04B3/462

    摘要： Apparatuses (and methods of manufacturing same), systems, and methods concerning polyphase digital filters are described. In one aspect, an apparatus is provided, including at least one pair of subfilters, each having symmetric coefficients, and a lattice comprising two adders and feedlines corresponding to each of the at least one pair of subfilters, each having symmetric coefficients. In one aspect, the apparatus is a polyphase finite impulse response (FIR) digital filter, including an interpolator and a decimator, where each of the interpolator and the decimator have at least one pair of subfilters, each having symmetric coefficients, and a lattice comprising two adders and feedlines corresponding to each of the at least one pair of subfilters, each having symmetric coefficients.

    DIGITAL MEASUREMENT INPUT FOR AN ELECTRIC AUTOMATION DEVICE, ELECTRIC AUTOMATION DEVICE COMPRISING A DIGITAL MEASUREMENT INPUT, AND METHOD FOR PROCESSING DIGITAL INPUT MEASUREMENT VALUES
    5.
    发明申请
    DIGITAL MEASUREMENT INPUT FOR AN ELECTRIC AUTOMATION DEVICE, ELECTRIC AUTOMATION DEVICE COMPRISING A DIGITAL MEASUREMENT INPUT, AND METHOD FOR PROCESSING DIGITAL INPUT MEASUREMENT VALUES 有权
    用于电动自动装置的数字测量输入，包含数字测量输入的电动自动化装置，以及用于处理数字输入测量值的方法

    公开(公告)号：US20160329975A1

    公开(公告)日：2016-11-10

    申请号：US15109874

    申请日：2014-01-22

    申请人： SIEMENS AKTIENGESELLSCHAFT

    发明人： ANDREAS JURISCH

    IPC分类号： H04B17/20 ,  H04L25/03 ,  H04B1/00 ,  G05B11/32 ,  H04B1/16

    CPC分类号： H04B17/20 ,  G01R19/2509 ,  G05B11/32 ,  G05B19/0423 ,  G05B2219/21126 ,  G05B2219/21137 ,  G05B2219/37533 ,  H04B1/0042 ,  H04B1/16 ,  H04L25/03834

    摘要： A digital measurement input for an electric automation device has a receiving device configured to receive digital input measurement values generated by sampling an analog measurement signal at a first sampling rate, and a signal converting device configured to generate digital output measurement values from the digital input measurement values and to provide digital output measurement values. The sampling rate and sampling times of each digital output measurement value is adapted to a specified sampling rate and/or specified sampling time. The signal converting device has a digital encoder filter on the input side and a digital decoder filter on the output side, between which an interpolator is provided. The encoder filter, the interpolator, and the decoder filter are matched to one another so as to adapt the sampling rate and/or sampling time of the digital input measurement values.

    摘要翻译： 电气自动化装置的数字测量输入具有接收装置，其被配置为接收以第一采样率对模拟测量信号进行采样而产生的数字输入测量值;以及信号转换装置，被配置为从数字输入测量值产生数字输出测量值 值并提供数字输出测量值。 每个数字输出测量值的采样率和采样时间都适用于指定的采样率和/或指定的采样时间。 信号转换装置在输入侧具有数字编码器滤波器，在输出侧具有数字解码器滤波器，在其之间提供内插器。 编码器滤波器，内插器和解码器滤波器彼此匹配，以便适应数字输入测量值的采样率和/或采样时间。

    Integrated mixed-signal ASIC with ADC, DAC, and DSP
    6.
    发明授权
    Integrated mixed-signal ASIC with ADC, DAC, and DSP 有权
    集成混合信号ASIC与ADC，DAC和DSP

    公开(公告)号：US09461732B2

    公开(公告)日：2016-10-04

    申请号：US14828126

    申请日：2015-08-17

    申请人： SEAKR ENGINEERING, INC.

    发明人： Erik Buehler ,  Damon Van Buren ,  Paul Rutt

    IPC分类号： H04B1/38 ,  H04B7/185

    CPC分类号： H04B7/18515 ,  H04B1/0039 ,  H04B1/0042 ,  H04B1/0046 ,  H04B1/44 ,  H04B7/08 ,  H04B7/1851 ,  H04B7/212

    摘要： An integrated analog to digital converting and digital to analog converting (ADDA) RF transceiver for satellite applications, configured to replace conventional analog RF down and up conversion circuitry. The ADDA RF transceiver includes one of more ADCs, DSPs, and DACs, all on a single ASIC. Further, the circuitry is to be radiation tolerant for high availability and reliability in the ionizing radiation environment present in the space environment.

    摘要翻译： 用于卫星应用的集成模数转换和数模转换（ADDA）RF收发器，配置为取代常规模拟RF下降转换电路。 ADDA RF收发器包括一个更多的ADC，DSP和DAC，都在单个ASIC上。 此外，该电路对于在空间环境中存在的电离辐射环境中的高可用性和可靠性是耐辐射的。

    Digital Calibration of Analog Distortion Using Split Analog Front-End
    7.
    发明申请
    Digital Calibration of Analog Distortion Using Split Analog Front-End 有权
    使用分路模拟前端的模拟失真数字校准

    公开(公告)号：US20140177768A1

    公开(公告)日：2014-06-26

    申请号：US13722429

    申请日：2012-12-20

    申请人： BROADCOM CORPORATION

    发明人： Frank van der Goes ,  Jan Roelof Westra

    IPC分类号： H04L27/00

    CPC分类号： H04L27/0002 ,  H04B1/0042 ,  H04B1/123

    摘要： A receiver is disclosed that is capable of correcting for harmonic distortion injected into received analog signals. The receiver splits the analog signal in the analog front-end and modifies the split analog signals with a difference signal. After amplification and/or sampling, the modified analog signals are recombined in a main data pathway and are kept separate in a secondary pathway. Utilizing the difference signal, a feedback loop that includes distorters and an LMS filter detects the distortion coefficient of the harmonic distortion. A distorter in the main data pathway utilizes the detected distortion coefficient to correct the harmonic distortion in the analog signal.

    摘要翻译： 公开了能够校正注入到接收的模拟信号中的谐波失真的接收机。 接收器将模拟前端的模拟信号分开，并用差分信号修改分离的模拟信号。 在放大和/或采样之后，修改的模拟信号在主数据通路中重组，并在次级途径中保持分离。 利用差分信号，包括不变频器和LMS滤波器的反馈回路检测谐波失真的失真系数。 主数据通道中的变形器利用检测到的失真系数来校正模拟信号中的谐波失真。

    Interface concept for the exchange of digital signals between an rf ic and a baseband ic
    8.
    发明申请
    Interface concept for the exchange of digital signals between an rf ic and a baseband ic 审中-公开
    用于在rf ic和基带ic之间交换数字信号的接口概念

    公开(公告)号：US20030147459A1

    公开(公告)日：2003-08-07

    申请号：US10258046

    申请日：2002-10-18

    发明人： Roland Egon Ryter

    IPC分类号： H04B001/38

    CPC分类号： H04B1/0042 ,  H04B1/0003 ,  H04B1/001 ,  H04B1/04 ,  H04B1/28 ,  H04B1/406

    摘要： The invention relates to a circuit arrangement which is provided with an analog receive and transmit unit which includes at least one A/D converter 13 and at least one D/A converter 14 for the conversion of signals, and also with a digital processing unit for the processing of digital signals. The invention also relates to a user set for mobile communication which includes a circuit arrangement of this kind and to a method for the transmission of digital signals between an analog receive and transmit unit and a digital processing unit. A circuit arrangement is proposed in which a reliable transmission of digital signals between a digital processing unit and an analog receive and transmit unit can be realized with little effort; to this end, it is proposed to provide a storage unit 17 and an interface 18, 19 which are arranged for the exchange of digital signals between the analog receive and transmit unit and the digital processing unit, the signal or data exchange between the receive and transmit unit and the digital processing unit taking place exclusively in the transmit and receive gaps 43.

    摘要翻译： 本发明涉及一种具有模拟接收和发射单元的电路装置，该模拟接收和发射单元包括用于信号转换的至少一个A / D转换器13和至少一个D / A转换器14，并且还包括用于 处理数字信号。 本发明还涉及一种用于移动通信的用户组，其包括这种电路装置以及用于在模拟接收和发射单元与数字处理单元之间传输数字信号的方法。 提出了一种电路装置，其中数字处理单元和模拟接收和发送单元之间的数字信号的可靠传输可以很少地实现; 为此，提出了一种存储单元17和接口18,19，其被布置用于在模拟接收和发送单元与数字处理单元之间交换数字信号，在接收和发送单元之间的信号或数据交换 发送单元和数字处理单元仅发生在发送和接收间隙43中。

    Digital intensive hybrid ADC/filter for LNA-free adaptive radio front-ends
    10.
    发明授权
    Digital intensive hybrid ADC/filter for LNA-free adaptive radio front-ends 有权
    数字强度混合ADC /滤波器，用于无LNA自适应无线电前端

    公开(公告)号：US09584164B1

    公开(公告)日：2017-02-28

    申请号：US15049616

    申请日：2016-02-22

    申请人： Intel Corporation

    发明人： Farhana Sheikh ,  Amy L. Whitcombe ,  Erkan Alpman ,  Yanjie Wang ,  Shreyas Sen

    IPC分类号： H04B1/00 ,  H04B1/10 ,  H04L27/00

    CPC分类号： H04B1/0042 ,  H04B1/10 ,  H04L27/0002

    摘要： A mixer-first receiver operates to generate filtering and analog-to-digital conversion concurrently and adaptively, while removing an LNA before a mixer to enable integration with digital baseband circuits. A plurality of switching capacitor arrays are integrated with a hybrid analog-to-digital filtering component. Switching capacitor arrays of the plurality of switching capacitor arrays can be selectively modified to perform both the filtering operation and the conversion operation together. The same switch capacitors of a switching capacitor array can be utilized in one phase of a clock cycle for the filtering and in another phase of the clock cycle for the conversion.

    摘要翻译： 混频器第一接收机用于同时和自适应地产生滤波和模数转换，同时在混频器之前去除LNA以实现与数字基带电路的集成。 多个开关电容器阵列与混合模数转换组件集成。 可以选择性地修改多个开关电容器阵列的开关电容器阵列以一起执行滤波操作和转换操作。 开关电容器阵列的相同开关电容器可以在用于滤波的时钟周期的一个阶段中用于转换的时钟周期的另一个阶段。