EFFICIENT POLYPHASE ARCHITECTURE FOR INTERPOLATOR AND DECIMATOR

    公开(公告)号:US20180115329A1

    公开(公告)日:2018-04-26

    申请号:US15402651

    申请日:2017-01-10

    CPC classification number: H04B1/0042 H04B1/0046 H04B3/462

    Abstract: Apparatuses (and methods of manufacturing same), systems, and methods concerning polyphase digital filters are described. In one aspect, an apparatus is provided, including at least one pair of subfilters, each having symmetric coefficients, and a lattice comprising two adders and feedlines corresponding to each of the at least one pair of subfilters, each having symmetric coefficients. In one aspect, the apparatus is a polyphase finite impulse response (FIR) digital filter, including an interpolator and a decimator, where each of the interpolator and the decimator have at least one pair of subfilters, each having symmetric coefficients, and a lattice comprising two adders and feedlines corresponding to each of the at least one pair of subfilters, each having symmetric coefficients.

    EFFICIENT POLYPHASE ARCHITECTURE FOR INTERPOLATOR AND DECIMATOR

    公开(公告)号:US20210211144A1

    公开(公告)日:2021-07-08

    申请号:US17155723

    申请日:2021-01-22

    Abstract: Apparatuses (and methods of manufacturing same), systems, and methods concerning polyphase digital filters are described. In one aspect, an apparatus is provided, including at least one pair of subfilters, each having symmetric coefficients, and a lattice comprising two adders and feedlines corresponding to each of the at least one pair of subfilters, each having symmetric coefficients. In one aspect, the apparatus is a polyphase finite impulse response (FIR) digital filter, including an interpolator and a decimator, where each of the interpolator and the decimator have at least one pair of subfilters, each having symmetric coefficients, and a lattice comprising two adders and feedlines corresponding to each of the at least one pair of subfilters, each having symmetric coefficients.

    APPARATUS AND METHOD FOR PROXIMITY SENSING

    公开(公告)号:US20250035765A1

    公开(公告)日:2025-01-30

    申请号:US18767412

    申请日:2024-07-09

    Abstract: A system and a method are disclosed for proximity detection using a phased antenna array including multiple antenna elements. A method includes transmitting, via a first antenna element and a second antenna element among the multiple antenna elements, a transmission signal; determining, for the first antenna element, a first power of a first injected signal and a second power of a first reflected signal corresponding to the transmission signal; determining, for the second antenna element, a third power of a second injected signal and a fourth power of a second reflected signal corresponding to the transmission signal; calculating, for the first antenna element, a first power metric based on at least one of the first power of the first injected signal or the second power of the first reflected signal; calculating, for the second antenna element, a second power metric based on at least one of the third power of the second injected signal or the fourth power of the second reflected signal; comparing the first power metric with a first threshold value; comparing the second power metric with a second threshold value; and determining whether an object is detected within a proximity range of the phased antenna array, based on the comparison of at least one of the first power metric with the first threshold value or the second power metric with the second threshold value.

    EFFICIENT POLYPHASE ARCHITECTURE FOR INTERPOLATOR AND DECIMATOR

    公开(公告)号:US20200052726A1

    公开(公告)日:2020-02-13

    申请号:US16656971

    申请日:2019-10-18

    Abstract: Apparatuses (and methods of manufacturing same), systems, and methods concerning polyphase digital filters are described. In one aspect, an apparatus is provided, including at least one pair of subfilters, each having symmetric coefficients, and a lattice comprising two adders and feedlines corresponding to each of the at least one pair of subfilters, each having symmetric coefficients. In one aspect, the apparatus is a polyphase finite impulse response (FIR) digital filter, including an interpolator and a decimator, where each of the interpolator and the decimator have at least one pair of subfilters, each having symmetric coefficients, and a lattice comprising two adders and feedlines corresponding to each of the at least one pair of subfilters, each having symmetric coefficients.

    SYSTEM AND METHOD FOR PROVIDING FILTER/MIXER STRUCTURE FOR OFDM SIGNAL SEPARATION

    公开(公告)号:US20200235969A1

    公开(公告)日:2020-07-23

    申请号:US16842019

    申请日:2020-04-07

    Abstract: An apparatus includes a first mixer performing first mixing of an input signal with a digital carrier which rotates the input signal such that one end of a target bandwidth in the input signal is aligned with an edge of a first bandpass filter that performs a first filtering on the first mixed input signal; a second mixer performing a second mixing of the first filtered input signal with a digital carrier which rotates the first filtered input signal such that the opposite end of the target bandwidth is aligned with an edge of a passband of a second bandpass filter that performs a second filtering on the second mixed input signal; and a third mixer performing a third mixing on the second filtered input signal which rotates the second filtered input signal such that the target bandwidth returns to the target bandwidth prior to the first mixing.

    SYSTEM AND METHOD FOR MAXIMAL CODE POLARIZATION

    公开(公告)号:US20180375526A1

    公开(公告)日:2018-12-27

    申请号:US16118655

    申请日:2018-08-31

    Abstract: An apparatus and a method. The apparatus includes a plurality of polarization processors, including n inputs and n outputs, where n is an integer, wherein the plurality of polarization processors is configured to polarize channels with different bit-channel reliability; and at least one permutation processor, including n inputs and n outputs, wherein each of the at least one permutation processor is connected between two of the plurality of polarization processors, and connects the n outputs of a first of the two of the plurality of polarizations processors to the n inputs of a second of the two of the plurality of polarization processors between which each of the at least one permutation processor is connected in a permutation pattern, wherein at least one permutation processor is configured to not further polarize a bit channel.

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