公开(公告)号：US20240145479A1

公开(公告)日：2024-05-02

申请号：US18406345

申请日：2024-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： BYOUNGHAK HONG ,  SEUNGHYUN SONG ,  MYUNGGIL KANG ,  KANG-ILL SEO

IPC: H01L27/12 ,  G01R27/02 ,  H01L23/535

CPC classification number: H01L27/1203 ,  G01R27/02 ,  H01L23/535 ,  H01L27/1211

Abstract: Resistance measuring structures for a stacked integrated circuit device are provided. The resistance measuring structures may include a first Complementary Field Effect Transistor (CFET) stack, a second CFET stack, and a conductive connection. The first CFET may include a first upper transistor that includes a first upper drain region and a first lower transistor that is between the substrate and the first upper transistor and includes a first lower drain region. The second CFET may include a second upper transistor that includes a second upper drain region and a second lower transistor that is between the substrate and the second upper transistor and includes a second lower drain region. The conductive connection may electrically connect the first upper drain region and the second upper drain region.

公开(公告)号：US20210335779A1

公开(公告)日：2021-10-28

申请号：US17371494

申请日：2021-07-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： WOOCHEOL SHIN ,  MYUNGGIL KANG ,  MINYI KIM ,  SANGHOON LEE

IPC: H01L27/06 ,  H01L21/8234

Abstract: A resistor including a device isolation layer is described that includes a first active region and a second active region, a buried insulating layer, and an N well region. The N well region surrounds the first active region, the second active region, the device isolation layer and the buried insulating layer. A first doped region and a second doped region are disposed on the first active region and the second active region. The first doped region and the second doped region are in contact with the N well region and include n type impurities.

公开(公告)号：US20230144507A1

公开(公告)日：2023-05-11

申请号：US18148810

申请日：2022-12-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： WOOCHEOL SHIN ,  MYUNGGIL KANG ,  MINYI KIM ,  SANGHOON LEE

IPC: H01L27/06 ,  H01L21/8234

CPC classification number: H01L27/0629 ,  H01L21/823481 ,  H01L21/823431

Abstract: A resistor including a device isolation layer is described that includes a first active region and a second active region, a buried insulating layer, and an N well region. The N well region surrounds the first active region, the second active region, the device isolation layer and the buried insulating layer. A first doped region and a second doped region are disposed on the first active region and the second active region. The first doped region and the second doped region are in contact with the N well region and include n type impurities.

公开(公告)号：US20220367521A1

公开(公告)日：2022-11-17

申请号：US17382149

申请日：2021-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： BYOUNGHAK HONG ,  SEUNGHYUN SONG ,  MYUNGGIL KANG ,  KANG-ILL SEO

IPC: H01L27/12 ,  H01L23/535 ,  G01R27/02

Abstract: Resistance measuring structures for a stacked integrated circuit device are provided. The resistance measuring structures may include a first Complementary Field Effect Transistor (CFET) stack, a second CFET stack, and a conductive connection. The first CFET may include a first upper transistor that includes a first upper drain region and a first lower transistor that is between the substrate and the first upper transistor and includes a first lower drain region. The second CFET may include a second upper transistor that includes a second upper drain region and a second lower transistor that is between the substrate and the second upper transistor and includes a second lower drain region. The conductive connection may electrically connect the first upper drain region and the second upper drain region.

公开(公告)号：US20210028164A1

公开(公告)日：2021-01-28

申请号：US16784788

申请日：2020-02-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： WOOCHEOL SHIN ,  MYUNGGIL KANG ,  MINYI KIM ,  SANGHOON LEE

IPC: H01L27/06 ,  H01L21/8234

Abstract: A resistor including a device isolation layer is described that includes a first active region and a second active region, a buried insulating layer, and an N well region. The N well region surrounds the first active region, the second active region, the device isolation layer and the buried insulating layer. A first doped region and a second doped region are disposed on the first active region and the second active region. The first doped region and the second doped region are in contact with the N well region and include n type impurities.