公开(公告)号：US20240145479A1

公开(公告)日：2024-05-02

申请号：US18406345

申请日：2024-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： BYOUNGHAK HONG ,  SEUNGHYUN SONG ,  MYUNGGIL KANG ,  KANG-ILL SEO

IPC: H01L27/12 ,  G01R27/02 ,  H01L23/535

CPC classification number: H01L27/1203 ,  G01R27/02 ,  H01L23/535 ,  H01L27/1211

Abstract: Resistance measuring structures for a stacked integrated circuit device are provided. The resistance measuring structures may include a first Complementary Field Effect Transistor (CFET) stack, a second CFET stack, and a conductive connection. The first CFET may include a first upper transistor that includes a first upper drain region and a first lower transistor that is between the substrate and the first upper transistor and includes a first lower drain region. The second CFET may include a second upper transistor that includes a second upper drain region and a second lower transistor that is between the substrate and the second upper transistor and includes a second lower drain region. The conductive connection may electrically connect the first upper drain region and the second upper drain region.

公开(公告)号：US20220367521A1

公开(公告)日：2022-11-17

申请号：US17382149

申请日：2021-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： BYOUNGHAK HONG ,  SEUNGHYUN SONG ,  MYUNGGIL KANG ,  KANG-ILL SEO

IPC: H01L27/12 ,  H01L23/535 ,  G01R27/02

Abstract: Resistance measuring structures for a stacked integrated circuit device are provided. The resistance measuring structures may include a first Complementary Field Effect Transistor (CFET) stack, a second CFET stack, and a conductive connection. The first CFET may include a first upper transistor that includes a first upper drain region and a first lower transistor that is between the substrate and the first upper transistor and includes a first lower drain region. The second CFET may include a second upper transistor that includes a second upper drain region and a second lower transistor that is between the substrate and the second upper transistor and includes a second lower drain region. The conductive connection may electrically connect the first upper drain region and the second upper drain region.

公开(公告)号：US20240072060A1

公开(公告)日：2024-02-29

申请号：US18499258

申请日：2023-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： BYOUNGHAK HONG ,  SEUNGHYUN SONG ,  KI-IL KIM ,  GUNHO JO ,  KANG-ILL SEO

IPC: H01L27/12 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/088

CPC classification number: H01L27/1203 ,  H01L21/8221 ,  H01L21/823412 ,  H01L21/823456 ,  H01L21/84 ,  H01L27/088

Abstract: Nanosheet transistor devices are provided. A nanosheet transistor device includes a transistor stack that includes a lower nanosheet transistor having a first nanosheet width and a lower gate width. The transistor stack also includes an upper nanosheet transistor that is on the lower nanosheet transistor and that has a second nanosheet width and an upper gate width that are different from the first nanosheet width and the lower gate width, respectively. Related methods of forming a nanosheet transistor device are also provided.

公开(公告)号：US20160086841A1

公开(公告)日：2016-03-24

申请号：US14711394

申请日：2015-05-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEUNGHYUN SONG ,  Hyeon Kyun Noh ,  Taeyong Kwon ,  Sangsu Kim ,  Shigenobu Maeda ,  Krishna Bhuwalka ,  Uihui Kwon ,  Keunho Lee ,  Wonsok Lee

IPC: H01L21/762 ,  H01L29/10 ,  H01L21/02 ,  H01L29/06 ,  H01L21/308 ,  H01L29/66

CPC classification number: H01L21/76224 ,  H01L21/3086 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method for forming a pattern of a semiconductor device and a semiconductor device formed using the same are provided. The method includes forming a buffer layer on a substrate, forming a channel layer on the buffer layer, forming support patterns penetrating the channel layer, and forming channel fin patterns and a buffer pattern by patterning the channel layer and the buffer layer. The channel layer includes a material of which a lattice constant is different from that of the buffer layer, and each of the channel fin patterns has both sidewalls that are in contact with the support patterns and are opposite to each other.

Abstract translation: 提供了一种用于形成半导体器件的图案的方法和使用其形成的半导体器件。 该方法包括在衬底上形成缓冲层，在缓冲层上形成沟道层，形成穿透沟道层的支撑图案，并通过图案化沟道层和缓冲层形成沟道鳍图案和缓冲图案。 沟道层包括晶格常数与缓冲层的晶格常数不同的材料，并且每个沟道鳍图案具有与支撑图案接触并且彼此相对的两个侧壁。

公开(公告)号：US20240355824A1

公开(公告)日：2024-10-24

申请号：US18757829

申请日：2024-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： BYOUNGHAK HONG ,  SEUNGHYUN SONG

IPC: H01L27/092 ,  H01L21/8238 ,  H01L25/07 ,  H01L27/06 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L27/0922 ,  H01L21/82385 ,  H01L25/074 ,  H01L27/0688 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/42392

Abstract: Integrated circuit devices may include a lower transistor and an upper transistor stacked on a substrate, and the upper transistor may overlap the lower transistor. The upper transistor may include an upper gate structure, and the lower transistor may include a lower gate structure, and the upper gate structure and the lower gate structure may have different widths in a horizontal direction.

公开(公告)号：US20220367520A1

公开(公告)日：2022-11-17

申请号：US17380999

申请日：2021-07-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： BYOUNGHAK HONG ,  SEUNGHYUN SONG ,  KI-IL KIM ,  GUNHO JO ,  KANG-ILL SEO

IPC: H01L27/12 ,  H01L27/088 ,  H01L21/84 ,  H01L21/822 ,  H01L21/8234

Abstract: Nanosheet transistor devices are provided. A nanosheet transistor device includes a transistor stack that includes a lower nanosheet transistor having a first nanosheet width and a lower gate width. The transistor stack also includes an upper nanosheet transistor that is on the lower nanosheet transistor and that has a second nanosheet width and an upper gate width that are different from the first nanosheet width and the lower gate width, respectively. Related methods of forming a nanosheet transistor device are also provided.