公开(公告)号：US11429777B2

公开(公告)日：2022-08-30

申请号：US17213538

申请日：2021-03-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonji Park ,  Jeonghoon Ahn ,  Jihyung Kim ,  Jaehee Oh ,  Yunki Choi ,  Minguk Kang

IPC: G06F30/398 ,  G06F30/392 ,  H01L21/66 ,  G06F113/18 ,  G06F119/08 ,  G06F119/18

Abstract: A method of estimating warpage of an interposer and a method of manufacturing a semiconductor package by using the same are disclosed. The interposer includes a through electrode passing through a substrate, and a plurality of metal wiring layers and a plurality of insulating layers on the substrate, and the method of estimating warpage of an interposer includes: performing a temperature sweep test by using sample interposers, and measuring warpages according to temperatures; deriving a warpage slope, as a function of temperature, of each of the sample interposers; deriving a warpage model by linearly fitting the warpage slope with respect to an average pattern density of metal wiring layers in each of the sample interposers; and calculating a room temperature warpage reference value of the interposer based on the warpage model.

公开(公告)号：US11437374B2

公开(公告)日：2022-09-06

申请号：US17034296

申请日：2020-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shaofeng Ding ,  Minguk Kang ,  Jihyung Kim ,  Jeong Hoon Ahn ,  Haeri Yoo ,  Yun Ki Choi

IPC: H01L27/092 ,  H01L25/065 ,  H01L27/02 ,  H01L29/417 ,  H01L21/768 ,  H01L27/088 ,  H01L29/165 ,  H01L29/08 ,  B82Y10/00 ,  H01L29/66 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/775 ,  H01L21/8238 ,  H01L23/522 ,  H01L25/18 ,  H01L21/8234 ,  H01L27/108 ,  H01L27/11 ,  H01L23/485 ,  H01L23/48 ,  H01L29/78

Abstract: A semiconductor device includes a substrate including a logic cell region and a connection region, a dummy transistor on the connection region, an intermediate connection layer on the dummy transistor, a first metal layer on the intermediate connection layer, an etch stop layer between the intermediate connection layer and the first metal layer, a through contact below the first metal layer penetrating the connection region, an upper portion of the through contact protruding above the etch stop layer, and a protection insulating pattern on the etch stop layer covering the upper portion of the through contact. The protection insulating pattern covers an upper side surface of the through contact and a top surface of the through contact.

公开(公告)号：US20220035984A1

公开(公告)日：2022-02-03

申请号：US17213538

申请日：2021-03-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonji Park ,  Jeonghoon Ahn ,  Jihyung Kim ,  Jaehee Oh ,  Yunki Choi ,  Minguk Kang

IPC: G06F30/392 ,  H01L21/66 ,  G06F30/398 ,  G06F119/08 ,  G06F113/18 ,  G06F119/18

Abstract: A method of estimating warpage of an interposer and a method of manufacturing a semiconductor package by using the same are disclosed. The interposer includes a through electrode passing through a substrate, and a plurality of metal wiring layers and a plurality of insulating layers on the substrate, and the method of estimating warpage of an interposer includes: performing a temperature sweep test by using sample interposers, and measuring warpages according to temperatures; deriving a warpage slope, as a function of temperature, of each of the sample interposers; deriving a warpage model by linearly fitting the warpage slope with respect to an average pattern density of metal wiring layers in each of the sample interposers; and calculating a room temperature warpage reference value of the interposer based on the warpage model.