-
1.
公开(公告)号:US20240153565A1
公开(公告)日:2024-05-09
申请号:US18223278
申请日:2023-07-18
Applicant: Samsung Electronics Co., Ltd.
Inventor: Yongsung Cho , Daeseok Byeon , Minjeong Heo
CPC classification number: G11C16/24 , G11C16/0483 , G11C16/26
Abstract: A memory device includes a memory cell array, and a plurality of page buffer units, the page buffer units each including a sensing node, a data transfer node, a first transistor precharging the data transfer node, a second transistor connecting the sensing node to the data transfer node, a sensing latch connected to the data transfer node, a third transistor changing a data value of the sensing latch, and a fourth transistor connecting the third transistor to the data transfer node, wherein, during a sensing operation, in a first time period, the sensing node is precharged based on a first path through the first transistor, the data transfer node, and the fourth transistor, and in a second time period, a voltage of the sensing node is set to a threshold voltage according to a second path through the fourth transistor, the data transfer node, and the third transistor.
-
2.
公开(公告)号:US20240363172A1
公开(公告)日:2024-10-31
申请号:US18509021
申请日:2023-11-14
Applicant: Samsung Electronics Co., Ltd.
Inventor: Minjeong Heo , Jaehue Shin , Daeseok Byeon , Yongsung Cho
CPC classification number: G11C16/24 , G11C16/0483
Abstract: A nonvolatile memory device includes a plurality of tri-state latches, a sensing node circuit configured to electrically couple a sensing node therein to a bitline of the memory device, a transfer node circuit configured to electrically couple a transfer node therein to the plurality of tri-state latches, and a node connection circuit configured to electrically connect the transfer node to the sensing node. In addition, the transfer node circuit and the node connection circuit are collectively configured to simultaneously reflect data stored in at least two of the plurality of tri-state latches to the sensing node, in response to a dump sequence operation.
-