MEMORY DEVICE INCLUDING PAGE BUFFER CIRCUIT AND SSD INCLUDING THE MEMORY DEVICE, AND METHOD OF USING THE SAME

    公开(公告)号:US20240153565A1

    公开(公告)日:2024-05-09

    申请号:US18223278

    申请日:2023-07-18

    CPC classification number: G11C16/24 G11C16/0483 G11C16/26

    Abstract: A memory device includes a memory cell array, and a plurality of page buffer units, the page buffer units each including a sensing node, a data transfer node, a first transistor precharging the data transfer node, a second transistor connecting the sensing node to the data transfer node, a sensing latch connected to the data transfer node, a third transistor changing a data value of the sensing latch, and a fourth transistor connecting the third transistor to the data transfer node, wherein, during a sensing operation, in a first time period, the sensing node is precharged based on a first path through the first transistor, the data transfer node, and the fourth transistor, and in a second time period, a voltage of the sensing node is set to a threshold voltage according to a second path through the fourth transistor, the data transfer node, and the third transistor.

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