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公开(公告)号:US20210020495A1
公开(公告)日:2021-01-21
申请号:US17039431
申请日:2020-09-30
Applicant: Samsung Electronics Co., Ltd.
Inventor: Myeong-Dong LEE , KEUNNAM KIM , Dongryul LEE , Minseong CHOI , Jimin CHOI , YONG KWAN KIM , CHANGHYUN CHO , YOOSANG HWANG
IPC: H01L21/768 , H01L27/108 , H01L23/532 , H01L23/535
Abstract: According to some embodiments, a semiconductor device may include gate structures on a substrate; first and second impurity regions formed in the substrate and at both sides of each of the gate structures; conductive line structures provided to cross the gate structures and connected to the first impurity regions; and contact plugs connected to the second impurity regions, respectively. For each of the conductive line structures, the semiconductor device may include a first air spacer provided on a sidewall of the conductive line structure; a first material spacer provided between the conductive line structure and the first air spacer; and an insulating pattern provided on the air spacer. The insulating pattern may include a first portion and a second portion, and the second portion may have a depth greater than that of the first portion and defines a top surface of the air spacer.
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公开(公告)号:US20170125283A1
公开(公告)日:2017-05-04
申请号:US15334469
申请日:2016-10-26
Applicant: Samsung Electronics Co., Ltd.
Inventor: Myeong-Dong LEE , KEUNNAM KIM , Dongryul LEE , Minseong CHOI , Jimin CHOI , YONG KWAN KIM , CHANGHYUN CHO , YOOSANG HWANG
IPC: H01L21/768 , H01L23/532 , H01L23/535
CPC classification number: H01L21/7682 , H01L21/76805 , H01L21/76849 , H01L21/76895 , H01L23/5329 , H01L23/535 , H01L27/10814 , H01L27/10823 , H01L27/10855 , H01L27/10876
Abstract: According to some embodiments, a semiconductor device may include gate structures on a substrate; first and second impurity regions formed in the substrate and at both sides of each of the gate structures; conductive line structures provided to cross the gate structures and connected to the first impurity regions; and contact plugs connected to the second impurity regions, respectively. For each of the conductive line structures, the semiconductor device may include a first air spacer provided on a sidewall of the conductive line structure; a first material spacer provided between the conductive line structure and the first air spacer; and an insulating pattern provided on the air spacer. The insulating pattern may include a first portion and a second portion, and the second portion may have a depth greater than that of the first portion and defines a top surface of the air spacer.
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公开(公告)号:US20190157133A1
公开(公告)日:2019-05-23
申请号:US16238172
申请日:2019-01-02
Applicant: Samsung Electronics Co., Ltd.
Inventor: Myeong-Dong LEE , KEUNNAM KIM , Dongryul LEE , Minseong CHOI , Jimin CHOI , YONG KWAN KIM , CHANGHYUN CHO , YOOSANG HWANG
IPC: H01L21/768 , H01L23/535 , H01L27/108 , H01L23/532
CPC classification number: H01L21/7682 , H01L21/76805 , H01L21/76849 , H01L21/76895 , H01L23/5329 , H01L23/535 , H01L27/10814 , H01L27/10823 , H01L27/10855 , H01L27/10876
Abstract: According to some embodiments, a semiconductor device may include gate structures on a substrate; first and second impurity regions formed in the substrate and at both sides of each of the gate structures; conductive line structures provided to cross the gate structures and connected to the first impurity regions; and contact plugs connected to the second impurity regions, respectively. For each of the conductive line structures, the semiconductor device may include a first air spacer provided on a sidewall of the conductive line structure; a first material spacer provided between the conductive line structure and the first air spacer; and an insulating pattern provided on the air spacer. The insulating pattern may include a first portion and a second portion, and the second portion may have a depth greater than that of the first portion and defines a top surface of the air spacer.
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