公开(公告)号：US20230232619A1

公开(公告)日：2023-07-20

申请号：US17886731

申请日：2022-08-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hosun JUNG ,  Minwu KIM ,  Jungwoo SONG ,  Wonchul LEE

IPC: H01L27/108

CPC classification number: H01L27/10897 ,  H01L27/10814 ,  H01L27/10894

Abstract: A semiconductor memory device includes a substrate including memory cell, peripheral, and intermediate regions; a device isolation pattern; a partitioning pattern; bit lines extending in a first direction to a boundary between the intermediate and peripheral regions; storage node contacts on the memory cell region and filling a lower portion of a space between bit lines; landing pads on the storage node contacts; dummy storage node contacts on the intermediate region and filling a lower portion of a space between bit lines; dummy landing pads on the dummy storage node contacts; and a dam structure on the intermediate region, extending in the first direction, and having a bar shape, wherein the dummy landing pads are spaced apart from an edge of the dam structure in a second direction, and the dummy storage node contacts are in contact with the partitioning pattern.

公开(公告)号：US20230232612A1

公开(公告)日：2023-07-20

申请号：US18050179

申请日：2022-10-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanwoo Shin ,  Hyuckjin KANG ,  Donghwan LEE ,  Jeonil LEE ,  Minwu KIM ,  Jungwoo SONG

IPC: H01L29/94

CPC classification number: H01L27/10814 ,  H01L27/10885 ,  H01L27/10855

Abstract: A semiconductor device includes a bit line structure on a substrate, a lower contact plug on a portion of the substrate adjacent to the bit line structure, an upper contact plug including a first metal pattern on the lower contact plug and a second metal pattern contacting an upper surface and an upper sidewall of the first metal pattern, and a capacitor on the upper contact plug. The upper surface of the first metal pattern is above an upper surface of the bit line structure with respect to an upper surface of the substrate.