公开(公告)号：US10664195B2

公开(公告)日：2020-05-26

申请号：US15992230

申请日：2018-05-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye Ju Kim ,  Hyo Bong Son ,  Ml-Hyang Lee

IPC: G06F12/00 ,  G06F3/06 ,  G11C11/56 ,  G11C16/04 ,  H01L27/11582

Abstract: A memory device, as provided herein, may include an invalidation bit circuit and a cell array. In methods for controlling such memory devices, the invalidation bit circuit may receive an invalid control command from a memory controller to update the invalid bit data to one of first and second states different from each other, the invalidation bit circuit may receive a read control command from the memory controller and may provide an invalid signal when the invalid bit data is in the first state, the invalidation bit circuit may transmit a data request when the invalid bit data is in the second state, and the cell array may receive the data request and provide data.