公开(公告)号：US11334457B1

公开(公告)日：2022-05-17

申请号：US16839675

申请日：2020-04-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hohyun Shin ,  Jongwan Kim ,  Hyungi Kim ,  Hyunsung Shin ,  Dongmin Kim ,  Myeongo Kim ,  Kwangil Park ,  Youngsoo Sohn

IPC: G06F11/00 ,  G06F11/20 ,  G06F11/07 ,  G11C29/00 ,  G11C15/04 ,  G11C11/412

Abstract: A semiconductor memory device including a memory cell array and an error relief circuit may be provided. The memory cell array includes plurality of memory cells which store data and are coupled to a plurality of word-lines and a plurality of bit-lines. The error relief circuit includes a replacement memory. The error relief circuit receives a command and an address from an external device, stores a first data associated with a first address in the replacement memory in response to detecting a sequence of the consecutively received commands with respect to the first address, and inputs/outputs the first data associated with the first address through the replacement memory.