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    Memory device performing parallel calculation processing, operating method thereof, and operating method of memory controller controlling the memory device
    1.
    发明授权
    Memory device performing parallel calculation processing, operating method thereof, and operating method of memory controller controlling the memory device 有权

    公开(公告)号：US11416178B2

    公开(公告)日：2022-08-16

    申请号：US17014667

    申请日：2020-09-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyunsung Shin ,  Sanghyuk Kwon ,  Youngcheon Kwon ,  Sukhan Lee ,  Haesuk Lee

    IPC: G06F3/06 ,  G06N3/02

    Abstract: A memory device includes a memory bank including a plurality of banks, each including a memory cell array; a calculation logic including a plurality of processor-in-memory (PIM) circuits arranged in correspondence to the banks, each of the plurality of PIM circuits performing calculation processing using at least one selected from data provided from a host and information read from a corresponding bank among the banks; and a control logic configured to control a memory operation on the memory bank in response to a command and/or an address, each received from the host, or to control the calculation logic to perform the calculation processing, wherein reading operations are respectively performed in parallel on the banks for the calculation processing, offsets having different values are respectively configured for the banks, and information is read from different positions in respective memory cell arrays of the banks and provided to the PIM circuits.

    SEMICONDUCTOR MEMORY DEVICES
    2.
    发明公开
    SEMICONDUCTOR MEMORY DEVICES 审中-公开

    公开(公告)号：US20240012712A1

    公开(公告)日：2024-01-11

    申请号：US18169769

    申请日：2023-02-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jongcheol Kim ,  Hyunsung Shin ,  Hohyun Shin ,  Taeyoung Oh ,  Kyungsoo Ha

    IPC: G06F11/10 ,  G06F3/06 ,  G11C11/4096 ,  G11C11/408

    CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G11C11/4096 ,  G11C11/4082

    Abstract: A semiconductor memory device includes a memory cell array, a data input/output (I/O) buffer, an I/O gating circuit and a control logic circuit. The memory cell array includes a plurality of sub array blocks arranged in a first direction and a second direction. The data I/O buffer exchanges user data with a memory controller through I/O pads. The I/O gating circuit is connected to the data I/O buffer through data buses and connected to the memory cell array through data I/O lines, and programs mapping relationship between the sub array blocks and the I/O pads, based on a mapping control signal such that uncorrectable errors that are detected by an error correction code engine in the memory controller are reduced. The control logic circuit generates the mapping control signal based on identifier information indicating a type of a central processing unit of the memory controller.

    SEMICONDUCTOR MEMORY DEVICES
    4.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES 有权

    公开(公告)号：US20240371417A1

    公开(公告)日：2024-11-07

    申请号：US18771859

    申请日：2024-07-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jongcheol Kim ,  Hyunsung Shin ,  Hohyun Shin ,  Taeyoung Oh ,  Kyungsoo Ha

    IPC: G11C7/10 ,  G06F3/06 ,  G06F11/10 ,  G11C11/408 ,  G11C11/4093 ,  G11C11/4096

    Abstract: A semiconductor memory device includes a memory cell array, a data input/output (I/O) buffer, an I/O gating circuit and a control logic circuit. The memory cell array includes a plurality of sub array blocks arranged in a first direction and a second direction. The data VO buffer exchanges user data with a memory controller through I/O pads. The I/O gating circuit is connected to the data I/O buffer through data buses and connected to the memory cell array through data I/O lines, and programs mapping relationship between the sub array blocks and the I/O pads, based on a mapping control signal such that uncorrectable errors that are detected by an error correction code engine in the memory controller are reduced. The control logic circuit generates the mapping control signal based on identifier information indicating a type of a central processing unit of the memory controller.

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