公开(公告)号：US11487615B2

公开(公告)日：2022-11-01

申请号：US17205276

申请日：2021-03-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiheung Kim ,  Hyungi Kim ,  Junhyung Kim ,  Sungchul Park ,  Yesin Ryu

IPC: G06F11/10 ,  G11C11/4096 ,  G11C11/406 ,  G11C11/408 ,  H01L25/065

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a scrubbing control circuit and a control logic circuit. The memory cell array includes memory cell rows, and each of the memory cell rows including volatile memory cells. The scrubbing control circuit generates scrubbing addresses for performing a normal scrubbing operation on the memory cell rows with a first period based on refresh row addresses for refreshing the memory cell rows. The control logic circuit controls the ECC engine the scrubbing control circuit to distribute a scrubbing operation on weak codewords dynamically within the refresh operation such that a dynamic allocated scrubbing (DAS) operation is performed with a second period smaller than the first period. An error bit is detected in each of the weak codewords during the normal scrubbing operation or normal read operation on at least one of the memory cell rows.

公开(公告)号：US11334457B1

公开(公告)日：2022-05-17

申请号：US16839675

申请日：2020-04-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hohyun Shin ,  Jongwan Kim ,  Hyungi Kim ,  Hyunsung Shin ,  Dongmin Kim ,  Myeongo Kim ,  Kwangil Park ,  Youngsoo Sohn

IPC: G06F11/00 ,  G06F11/20 ,  G06F11/07 ,  G11C29/00 ,  G11C15/04 ,  G11C11/412

Abstract: A semiconductor memory device including a memory cell array and an error relief circuit may be provided. The memory cell array includes plurality of memory cells which store data and are coupled to a plurality of word-lines and a plurality of bit-lines. The error relief circuit includes a replacement memory. The error relief circuit receives a command and an address from an external device, stores a first data associated with a first address in the replacement memory in response to detecting a sequence of the consecutively received commands with respect to the first address, and inputs/outputs the first data associated with the first address through the replacement memory.

公开(公告)号：US11194653B2

公开(公告)日：2021-12-07

申请号：US16668090

申请日：2019-10-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yesin Ryu ,  Sanguhn Cha ,  Hyungi Kim ,  Hoon Shin

IPC: G06F11/10 ,  G11C29/42

Abstract: A semiconductor memory device and a memory system including the same are provided. The semiconductor memory device includes a memory cell array including memory blocks, a local parity memory block, and a register block. The memory blocks respectively store pieces of partial local data in response to a plurality of column selection signals, or a first partial global parity in response to a global parity column selection signal. The local parity memory block stores local parities of local data in response to the plurality of column selection signals, or a second partial global parity in response to the global parity column selection signal. The register block generates a global parity including the first partial global parities and the second partial global parity. Each piece of local data includes the partial local data, and the global parity is a parity of the pieces of local data and the local parities.

公开(公告)号：US20200319960A1

公开(公告)日：2020-10-08

申请号：US16668090

申请日：2019-10-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yesin RYU ,  Sanguhn Cha ,  Hyungi Kim ,  Hoon Shin

IPC: G06F11/10 ,  G11C29/42

Abstract: A semiconductor memory device and a memory system including the same are provided. The semiconductor memory device includes a memory cell array including memory blocks, a local parity memory block, and a register block. The memory blocks respectively store pieces of partial local data in response to a plurality of column selection signals, or a first partial global parity in response to a global parity column selection signal. The local parity memory block stores local parities of local data in response to the plurality of column selection signals, or a second partial global parity in response to the global parity column selection signal. The register block generates a global parity including the first partial global parities and the second partial global parity. Each piece of local data includes the partial local data, and the global parity is a parity of the pieces of local data and the local parities.