公开(公告)号：US20180081692A1

公开(公告)日：2018-03-22

申请号：US15654277

申请日：2017-07-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-hun LEE ,  Jae-un PARK ,  Si-hoon SONG ,  Myung-sun KIM

IPC: G06F9/38 ,  G06F9/30 ,  G06F15/82

CPC classification number: G06F9/3853 ,  G06F8/41 ,  G06F8/4441 ,  G06F9/3001 ,  G06F9/30072 ,  G06F9/30079 ,  G06F9/30152 ,  G06F9/30181 ,  G06F9/3885 ,  G06F15/82

Abstract: An electronic apparatus generating compiled data used in a very long instruction word (VLIW) processor including a plurality of function units is provided. The electronic apparatus includes a storage and a processor configured to control the storage to store the compiled data in which a plurality of VLIW instructions are compiled, identify a VLIW instruction from the compiled data; and update, if a multi-cycle no operation (nop) instruction for the plurality of function units is identified within a cycle corresponding to a latency of the identified VLIW instruction and if an end cycle of another VLIW instruction is within the cycle corresponding to the latency of the identified VLIW instruction, the compiled data by including information on a cycle difference between an end cycle of the identified VLIW instruction and the end cycle of the another VLIW instruction in the multi-cycle nop instruction.

公开(公告)号：US20180088954A1

公开(公告)日：2018-03-29

申请号：US15655466

申请日：2017-07-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeon-bok LEE ,  Myung-sun KIM ,  Shin-gyu KIM

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3836 ,  G06F8/4451 ,  G06F9/3001 ,  G06F9/3017 ,  G06F9/3885

Abstract: An electronic apparatus is provided for obtaining compiling data used in an external processor including a function unit including a plurality of input ports. The electronic apparatus includes a storage configured to store a plurality of instructions, and a processor configured to schedule each of the plurality of instructions in a plurality of cycles, assign a plurality of input data corresponding to the plurality of instructions to the plurality of input ports in a corresponding cycle, and if an unassigned input port among the plurality of input ports is present in a first cycle, assign a part of input data corresponding to an instruction scheduled in a second cycle after the first cycle to the unassigned input port in the first cycle, and obtain the compiling data by assigning remaining data of the input data corresponding the instruction to one of the plurality of input ports in the second cycle.