公开(公告)号：US12141478B2

公开(公告)日：2024-11-12

申请号：US17932734

申请日：2022-09-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Deokho Seo ,  Taekyeong Ko ,  Namhyung Kim ,  Daejeong Kim ,  Dohan Kim ,  Hoyoung Lee ,  Insu Choi

IPC: G06F3/06 ,  H03M13/00 ,  H03M13/11

Abstract: A memory device includes a memory cell array including a normal region in which first data is stored and a parity region in which a parity bit for the data is stored, and an error correction code (ECC) engine. The ECC engine is configured to determine whether there is an error in the first data based on the first data and the parity bit, and to output, in response to receiving an uncorrected read command from a memory controller, second data in a state in which an error bit in the first data is not corrected.

公开(公告)号：US11670355B2

公开(公告)日：2023-06-06

申请号：US17406511

申请日：2021-08-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minsu Kim ,  Namhyung Kim ,  Daejeong Kim ,  Dohan Kim ,  Chanik Park ,  Deokho Seo ,  Wonjae Shin ,  Changmin Lee ,  Ilguy Jung ,  Insu Choi

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/4096

CPC classification number: G11C11/40615 ,  G11C11/4076 ,  G11C11/4096 ,  G11C11/40618

Abstract: Provided are an accelerator controlling a memory device, a computing system including the accelerator, and an operating method of the accelerator. The accelerator includes: a signal control/monitoring circuit configured to detect an entry to a self-refresh mode of a memory device and an exit from the self-refresh mode based on monitoring a signal provided from a host; an accelerator logic configured to generate a first command/address signal and a first piece of data; and a selector configured to output the first command/address signal and the first piece of data to the memory device based on detection of the entry to the self-refresh mode, and output a second command/address signal and a second piece of data provided from the host, to the memory device, based on detection of the exit from the self-refresh mode.

公开(公告)号：US11301209B2

公开(公告)日：2022-04-12

申请号：US16843199

申请日：2020-04-08

Applicant: Samsung Electronics Co., Ltd. ,  Seoul National University R&DB Foundation

Inventor： Seungwon Lee ,  Namhyung Kim ,  Hanmin Park ,  Kiyoung Choi

IPC: G06F7/544 ,  G06N3/02 ,  G06F7/02 ,  G06F7/74

Abstract: A processor-implemented method of processing neural network data includes: setting first limit data by performing a first operation based on first input data and weight data generated from weights included in a filter; comparing the first limit data with an intermediate result of a second operation performed based on second input data and the weight data; and determining whether to perform a subsequent second operation based on a result of the comparing.

公开(公告)号：US10819381B2

公开(公告)日：2020-10-27

申请号：US16449765

申请日：2019-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangbong Lee ,  Namhyung Kim ,  Taekon Kim ,  Kiyul Lim ,  Jaehoon Lee

IPC: G06F3/02 ,  H04B1/3888 ,  H04M1/02 ,  G06F1/16

Abstract: An electronic device according to certain embodiments includes a housing, a first glass plate coupled to the housing and defining an inner space, the first glass plate including a peripheral portion including: a first, second, third, fourth, and fifth surface forming an edge of the glass plate, the first and fifth surfaces being substantially parallel and the third surface being substantially perpendicular to the first and fifth surfaces, a decorative layer formed of a first material, disposed on a first area of the fifth surface such that a second area disposed between the fourth surface and the first area is uncovered by the decorative layer, and a protective layer formed of a second material, covering the second surface, the third surface, the fourth surface, the second area of the fifth surface, and a part of the decorative layer.

公开(公告)号：US12232350B2

公开(公告)日：2025-02-18

申请号：US17749734

申请日：2022-05-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jonghwan Choi ,  Namhyung Kim ,  Jihoon Kang ,  Seokki Kim ,  Chijoon Kim ,  Changyong Seo ,  Wonho Lee ,  Soonwan Chung

IPC: G06F1/16 ,  C09K3/10 ,  H10K50/842 ,  H10K59/12

Abstract: Disclosed is a foldable electronic device including a sealing member for protecting a side surface of flexible display. A foldable electronic device according to various embodiments of the disclosure may include: a foldable housing configured to be folded and unfolded, a flexible display disposed in the foldable housing, the flexible display including a display panel configured to display image information and a cover window covering a first surface of the display panel on which image information is displayed, the display panel having at least one portion configured to be bent according to folding and unfolding operations of the foldable housing, and a seal contacting a region of a side part of the flexible display with reference to the first surface of the flexible display, the region including a space between the cover window and the display panel, wherein the seal may include a polymer material which is configured to be bent according to the bending operation in a state of being in contact with a side surface of the flexible display during the bending operation of the flexible display.

公开(公告)号：US12205012B2

公开(公告)日：2025-01-21

申请号：US16550498

申请日：2019-08-26

Applicant: Samsung Electronics Co., Ltd ,  Seoul National University R&DB Foundation

Inventor： Seungwon Lee ,  Hanmin Park ,  Gunhee Lee ,  Namhyung Kim ,  Joonsang Yu ,  Kiyoung Choi

IPC: G06N3/063 ,  G06N3/04 ,  G06N3/084

Abstract: A method of accelerating a training process of a neural network includes acquiring activations used in the training process and a bit-vector corresponding to the activations, selecting activations requiring an operation from among the acquired activations by using the bit-vector, and performing backward propagation using the selected activations and filters corresponding to the selected activations.

公开(公告)号：US11721408B2

公开(公告)日：2023-08-08

申请号：US17388238

申请日：2021-07-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daejeong Kim ,  Namhyung Kim ,  Dohan Kim ,  Deokho Seo ,  Wonjae Shin ,  Insu Choi

IPC: G01R31/28 ,  G11C29/42 ,  G11C29/50 ,  G06F11/10

CPC classification number: G11C29/42 ,  G06F11/1068 ,  G11C29/50004 ,  G11C2029/5004

Abstract: A memory device includes a memory cell array and a test controller. The memory cell array includes a plurality of memory cells, where the memory cell array is divided into multiple regions. The test controller is configured to perform a parallel bit test (PBT) on the plurality of memory cells, where the test controller selects fail data including a fail data bit among internal data output from the multiple regions during the PBT, and outputs the fail data via a data input/output signal line to the outside of the memory device.

公开(公告)号：US11610624B2

公开(公告)日：2023-03-21

申请号：US17474666

申请日：2021-09-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minsu Kim ,  Namhyung Kim ,  Daejeong Kim ,  Dohan Kim ,  Chanik Park ,  Deokho Seo ,  Wonjae Shin ,  Changmin Lee ,  Ilguy Jung ,  Insu Choi

IPC: G11C11/406

Abstract: Provided are a memory device skipping a refresh operation and an operating method thereof. The memory device includes a memory cell array including N rows; a refresh controller configured to control a refresh operation for the N rows of the memory cell array based on a refresh command; and an access information storage circuit including a plurality of registers configured to store flag information corresponding to each of the N rows, wherein a first value indicates rows that have been accessed, and a second value indicates rows that have not been accessed. The refresh controller is further configured to control whether the refresh operation is performed for a first row of the N rows at a refresh timing for the first row based on the flag information corresponding to the first row.

公开(公告)号：US20220215871A1

公开(公告)日：2022-07-07

申请号：US17406511

申请日：2021-08-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minsu Kim ,  Namhyung Kim ,  Daejeong Kim ,  Dohan Kim ,  Chanik Park ,  Deokho Seo ,  Wonjae Shin ,  Changmin Lee ,  Ilguy Jung ,  Insu Choi

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/4096

Abstract: Provided are an accelerator controlling a memory device, a computing system including the accelerator, and an operating method of the accelerator. The accelerator includes: a signal control/monitoring circuit configured to detect an entry to a self-refresh mode of a memory device and an exit from the self-refresh mode based on monitoring a signal provided from a host; an accelerator logic configured to generate a first command/address signal and a first piece of data; and a selector configured to output the first command/address signal and the first piece of data to the memory device based on detection of the entry to the self-refresh mode, and output a second command/address signal and a second piece of data provided from the host, to the memory device, based on detection of the exit from the self-refresh mode.

公开(公告)号：US10255182B2

公开(公告)日：2019-04-09

申请号：US15019368

申请日：2016-02-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Namhyung Kim ,  Junwhan Ahn ,  Kiyoung Choi ,  Woong Seo

IPC: G06F12/00 ,  G06F12/0811 ,  G06F12/0862

Abstract: A method of managing a cache includes storing first data of an upper level cache in a lower level cache, predicting a reuse distance level of second data having a same signature as the first data based on access information about the first data, and storing the second data in one of the lower level cache and a main memory based on the predicted reuse distance level of the second data.