公开(公告)号：US20030058053A1

公开(公告)日：2003-03-27

申请号：US10253072

申请日：2002-09-24

申请人： Samsung Electronics Co., Ltd.

发明人： Phil-Jae Jeon ,  Myoung-Su Lee

IPC分类号： H03L007/00

CPC分类号： H03C3/0975 ,  H03C3/0958 ,  H03L7/0996 ,  H03L7/0998 ,  H03L7/18

摘要： A phase locked loop (PLL) for reducing electromagnetic interference (EMI) is provided. The PLL is not sensitive to a manufacturing process, consumes less power, occupies a small layout space, and can flexibly control a modulation frequency and a modulation rate flexibly. The PLL for reducing the EMI controls the signals having a phase difference, which is n-times (where n is an integer) the basic delay time of the output signals from a voltage controlled oscillator (VCO), and determines the modulation rate. Then, the PLL repeats the procedure during the cycle of a pre-defined modulation frequency. The PLL for reducing the EMI not only reduces the EMI, but also does not require a ROM. Therefore, the layout space can be reduced and broad frequency ranges can be obtained. In addition, since the phase difference of the output signals of the VCO is controlled by logic circuits, the PLL is insensitive to changes in the manufacturing process.

摘要翻译： 提供了用于降低电磁干扰（EMI）的锁相环（PLL）。 PLL对制造过程不敏感，功耗较小，布局空间小，灵活控制调制频率和调制速率。 用于降低EMI的PLL控制具有来自压控振荡器（VCO）的输出信号的基本延迟时间的n倍（其中n是整数）的相位差的信号，并且确定调制率。 然后，PLL在预定义的调制频率的周期中重复该过程。 用于降低EMI的PLL不仅降低了EMI，而且不需要ROM。 因此，可以减小布局空间并且可以获得宽的频率范围。 此外，由于VCO的输出信号的相位差由逻辑电路控制，所以PLL对制造过程的变化不敏感。