公开(公告)号：US10372452B2

公开(公告)日：2019-08-06

申请号：US15615811

申请日：2017-06-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Paul E. Kitchin ,  Rama S. Gopal ,  Karthik Sundaram

IPC: G06F9/30 ,  G06F9/35 ,  G06F12/0875 ,  G06F9/38

Abstract: A system and a method to cascade execution of instructions in a load-store unit (LSU) of a central processing unit (CPU) to reduce latency associated with the instructions. First data stored in a cache is read by the LSU in response a first memory load instruction of two immediately consecutive memory load instructions. Alignment, sign extension and/or endian operations are performed on the first data read from the cache in response to the first memory load instruction, and, in parallel, a memory-load address-forwarded result is selected based on a corrected alignment of the first data read in response to the first memory load instruction to provide a next address for a second of the two immediately consecutive memory load instructions. Second data stored in the cache is read by the LSU in response to the second memory load instruction based on the selected memory-load address-forwarded result.

公开(公告)号：US10956155B2

公开(公告)日：2021-03-23

申请号：US16421463

申请日：2019-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Paul E. Kitchin ,  Rama S. Gopal ,  Karthik Sundaram

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/35 ,  G06F12/0875

Abstract: A system and a method to cascade execution of instructions in a load-store unit (LSU) of a central processing unit (CPU) to reduce latency associated with the instructions. First data stored in a cache is read by the LSU in response a first memory load instruction of two immediately consecutive memory load instructions. Alignment, sign extension and/or endian operations are performed on the first data read from the cache in response to the first memory load instruction, and, in parallel, a memory-load address-forwarded result is selected based on a corrected alignment of the first data read in response to the first memory load instruction to provide a next address for a second of the two immediately consecutive memory load instructions. Second data stored in the cache is read by the LSU in response to the second memory load instruction based on the selected memory-load address-forwarded result.

公开(公告)号：US10275217B2

公开(公告)日：2019-04-30

申请号：US15612963

申请日：2017-06-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Rama S. Gopal ,  Paul E. Kitchin ,  Karthik Sundaram

IPC: G06F7/38 ,  G06F7/485 ,  G06F7/50

Abstract: According to one general aspect, a load unit may include a load circuit configured to load at least one piece of data from a memory. The load unit may include an alignment circuit configured to align the data to generate an aligned data. The load unit may also include a mathematical operation execution circuit configured to generate a resultant of a predetermined mathematical operation with the at least one piece of data as an operand. Wherein the load unit is configured to, if an active instruction is associated with the predetermined mathematical operation, bypass the alignment circuit and input the piece of data directly to the mathematical operation execution circuit.