公开(公告)号：US10891135B2

公开(公告)日：2021-01-12

申请号：US16294916

申请日：2019-03-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Paul E. Kitchin ,  Nicholas Humphries ,  Ken Yu Lim ,  Ryan Hensley

IPC: G06F9/38 ,  G06F9/30 ,  G06F12/0875

Abstract: A system and a method are disclosed to process instructions in an execution unit (EU) that includes an operand cache (OC). The OC stores a copy of at least one frequently used operand stored in a physical register file (PRF). The EU may process instructions using operands obtained from the PRF or from the OC. In the first mode, an OC renaming unit (OC-REN) indicates to the EU to process instructions using operands obtained from the OC if processing the instructions using operands obtained from the OC uses less power than using operands obtained from the PRF. In the second mode, the OC-REN indicates to the EU to process the instructions using operands obtained from the PRF if processing the instructions using operands obtained from the PRF uses less power than using operands obtained from the OC.

公开(公告)号：US10372452B2

公开(公告)日：2019-08-06

申请号：US15615811

申请日：2017-06-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Paul E. Kitchin ,  Rama S. Gopal ,  Karthik Sundaram

IPC: G06F9/30 ,  G06F9/35 ,  G06F12/0875 ,  G06F9/38

Abstract: A system and a method to cascade execution of instructions in a load-store unit (LSU) of a central processing unit (CPU) to reduce latency associated with the instructions. First data stored in a cache is read by the LSU in response a first memory load instruction of two immediately consecutive memory load instructions. Alignment, sign extension and/or endian operations are performed on the first data read from the cache in response to the first memory load instruction, and, in parallel, a memory-load address-forwarded result is selected based on a corrected alignment of the first data read in response to the first memory load instruction to provide a next address for a second of the two immediately consecutive memory load instructions. Second data stored in the cache is read by the LSU in response to the second memory load instruction based on the selected memory-load address-forwarded result.

公开(公告)号：US10956155B2

公开(公告)日：2021-03-23

申请号：US16421463

申请日：2019-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Paul E. Kitchin ,  Rama S. Gopal ,  Karthik Sundaram

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/35 ,  G06F12/0875

Abstract: A system and a method to cascade execution of instructions in a load-store unit (LSU) of a central processing unit (CPU) to reduce latency associated with the instructions. First data stored in a cache is read by the LSU in response a first memory load instruction of two immediately consecutive memory load instructions. Alignment, sign extension and/or endian operations are performed on the first data read from the cache in response to the first memory load instruction, and, in parallel, a memory-load address-forwarded result is selected based on a corrected alignment of the first data read in response to the first memory load instruction to provide a next address for a second of the two immediately consecutive memory load instructions. Second data stored in the cache is read by the LSU in response to the second memory load instruction based on the selected memory-load address-forwarded result.

公开(公告)号：US10275217B2

公开(公告)日：2019-04-30

申请号：US15612963

申请日：2017-06-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Rama S. Gopal ,  Paul E. Kitchin ,  Karthik Sundaram

IPC: G06F7/38 ,  G06F7/485 ,  G06F7/50

Abstract: According to one general aspect, a load unit may include a load circuit configured to load at least one piece of data from a memory. The load unit may include an alignment circuit configured to align the data to generate an aligned data. The load unit may also include a mathematical operation execution circuit configured to generate a resultant of a predetermined mathematical operation with the at least one piece of data as an operand. Wherein the load unit is configured to, if an active instruction is associated with the predetermined mathematical operation, bypass the alignment circuit and input the piece of data directly to the mathematical operation execution circuit.

公开(公告)号：US09274970B2

公开(公告)日：2016-03-01

申请号：US14307444

申请日：2014-06-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Paul E. Kitchin

IPC: G06F12/00 ,  G06F12/08

CPC classification number: G06F12/0875 ,  G06F9/3834 ,  G06F9/3836 ,  G06F12/0831

Abstract: According to one general aspect, an apparatus may include an instruction fetch unit, an execution unit, and a cache resynchronization predictor, as described above. The instruction fetch unit may be configured to issue a first memory read operation to a memory address, and a first memory write operation to the memory address, wherein the first memory read operation is stored at an instruction address. The execution unit may be configured to execute the first memory read operation, wherein the execution of the first memory read operation causes a resynchronization exception. The cache resynchronization predictor may be configured to associate the instruction address with a resynchronization exception, and determine if a memory read operation stored at the instruction address comprises a resynchronization predicted store.

Abstract translation: 根据一个一般方面，如上所述，装置可以包括指令获取单元，执行单元和高速缓存再同步预测器。 指令提取单元可以被配置为向存储器地址发出第一存储器读取操作以及对存储器地址的第一存储器写入操作，其中第一存储器读取操作存储在指令地址处。 执行单元可以被配置为执行第一存储器读取操作，其中执行第一存储器读取操作引起重新同步异常。 缓存重新同步预测器可以被配置为将指令地址与重新同步异常相关联，并且确定存储在指令地址处的存储器读取操作是否包括重新同步预测存储。