公开(公告)号：US10725432B2

公开(公告)日：2020-07-28

申请号：US16040963

申请日：2018-07-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chih-Wei Yao ,  Ronghua Ni

IPC: G04F10/00 ,  H03L7/091 ,  H03M1/12 ,  H03L7/089 ,  H03L7/099 ,  H03M1/48

Abstract: A system and method for fast converging gain calibration for phase lock loops (PLL) are herein disclosed. According to one embodiment, a method includes receiving, with a voltage generation circuit, an input value representing a difference between a sampled voltage and a reference voltage, and adjusting, with the voltage generation circuit, the reference voltage by generating a voltage output based on the difference represented by the input value.

公开(公告)号：US11175633B2

公开(公告)日：2021-11-16

申请号：US16935827

申请日：2020-07-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chih-Wei Yao ,  Ronghua Ni

IPC: G04F10/00 ,  H03L7/091 ,  H03M1/12 ,  H03L7/089 ,  H03L7/099 ,  H03M1/48

Abstract: A system and method for fast converging gain calibration for phase lock loops (PLL) are herein disclosed. According to one embodiment, a method includes receiving, with a voltage generation circuit, an input value representing a difference between a sampled voltage and a reference voltage, and adjusting, with the voltage generation circuit, the reference voltage by generating a voltage output based on the difference represented by the input value.

公开(公告)号：US10996634B2

公开(公告)日：2021-05-04

申请号：US16040963

申请日：2018-07-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chih-Wei Yao ,  Ronghua Ni

IPC: G04F10/00 ,  H03L7/091 ,  H03M1/12 ,  H03L7/089 ,  H03L7/099 ,  H03M1/48

Abstract: A system and method for fast converging gain calibration for phase lock loops (PLL) are herein disclosed. According to one embodiment, a method includes receiving, with a voltage generation circuit, an input value representing a difference between a sampled voltage and a reference voltage, and adjusting, with the voltage generation circuit, the reference voltage by generating a voltage output based on the difference represented by the input value.

公开(公告)号：US20190212703A1

公开(公告)日：2019-07-11

申请号：US16040963

申请日：2018-07-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chih-Wei YAO ,  Ronghua Ni

IPC: G04F10/00 ,  H03L7/091 ,  H03L7/099 ,  H03L7/089 ,  H03M1/12

Abstract: A system and method for fast converging gain calibration for phase lock loops (PLL) are herein disclosed. According to one embodiment, a method includes receiving, with a voltage generation circuit, an input value representing a difference between a sampled voltage and a reference voltage, and adjusting, with the voltage generation circuit, the reference voltage by generating a voltage output based on the difference represented by the input value.