公开(公告)号：US20250125998A1

公开(公告)日：2025-04-17

申请号：US18401971

申请日：2024-01-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsoo CHOI ,  Hiep PHAM ,  Chih-Wei YAO ,  Hyojun KIM

IPC: H04L25/02

Abstract: A wireline transceiver system includes a predriver configured to generate a signal; a source-series termination (SST) driver configured to receive the generated signal; and a replica driver configured to continuously generate bias voltages in real time to modulate current of a push-pull current source of the SST driver based on a voltage of the received signal across a process, voltage, and temperature (PVT) range.

公开(公告)号：US20210067145A1

公开(公告)日：2021-03-04

申请号：US16835778

申请日：2020-03-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Xiong LIU ,  Chih-Wei YAO

IPC: H03K3/03 ,  H03K3/012

Abstract: A ring voltage controlled oscillator (VCO) circuit is herein provided. According to one embodiment, a ring VCO circuit includes a plurality of stages connected in series, wherein each stage includes a first inverter, a second inverter, a third inverter and a fourth inverter, the first inverter connected in parallel with the third and fourth inverters and the second inverter connected in parallel with the third and fourth inverters, and a first biasing resistor connected to a first node and coupled to an input of the first inverter. The first biasing resistor includes a first switch configured to set the first biasing resistor to about zero voltage

公开(公告)号：US20200099380A1

公开(公告)日：2020-03-26

申请号：US16220898

申请日：2018-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Zhiqiang HUANG ,  Chih-Wei YAO ,  Hiep PHAM

IPC: H03L7/087 ,  H03L7/10 ,  H03L7/08 ,  H04L27/227

Abstract: A synchronized in-phase/quadrature phase (I/Q) detection circuit and a method of the same are provided. The synchronized I/Q detection circuit includes a first logic circuit; a first filter; a first reset and sampling circuit; a first multiplexer; a second logic circuit; a second filter; a second reset and sampling circuit; a signal generator; and a comparator.

公开(公告)号：US20250125815A1

公开(公告)日：2025-04-17

申请号：US18409000

申请日：2024-01-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsoo CHOI ,  Hiep PHAM ,  Chih-Wei YAO ,  Hyojun KIM

IPC: H03M1/68

Abstract: A hybrid digital-to-analog converter (DAC) driver is provided. The hybrid DAC driver includes an upper DAC stage configured to receive an upper set of bits of a digital signal, the upper DAC stage comprising an upper set of DAC units, with a first DAC unit in the upper set of DAC units having a different weight than a second DAC unit in the upper set of DAC units; a lower DAC stage configured to receive a lower set of bits of the digital signal, the lower DAC stage comprising a lower set of DAC units formed in an R-2R resistor ladder network; and an output stage for outputting an analog signal from the upper DAC stage and the lower DAC stage.

公开(公告)号：US20200348626A1

公开(公告)日：2020-11-05

申请号：US16935827

申请日：2020-07-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chih-Wei YAO ,  Ronghua NI

IPC: G04F10/00 ,  H03L7/091 ,  H03L7/089 ,  H03M1/48 ,  H03L7/099 ,  H03M1/12

Abstract: A system and method for fast converging gain calibration for phase lock loops (PLL) are herein disclosed. According to one embodiment, a method includes receiving, with a voltage generation circuit, an input value representing a difference between a sampled voltage and a reference voltage, and adjusting, with the voltage generation circuit, the reference voltage by generating a voltage output based on the difference represented by the input value.

公开(公告)号：US20200177173A1

公开(公告)日：2020-06-04

申请号：US16786364

申请日：2020-02-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wanghua WU ,  Chih-Wei YAO

IPC: H03K5/156 ,  H03L7/099 ,  H03L7/097 ,  H04L25/49 ,  H03L7/08 ,  H03L7/091

Abstract: A system and method for fast converging reference clock duty cycle correction for a digital to time converter (DTC) based analog fractional-N phase-locked loop (PLL) are herein disclosed. According to one embodiment, an electronic circuit includes a clock doubler, a comparator that outputs a value representing a difference between a voltage at a voltage-to-current (Gm) circuit and a reference voltage that is adjusted to compensate for an offset of the comparator, and a duty cycle calibration circuit that receives the value output from the comparator and adjusts a duty cycle of the PLL by extracting an error from the value output from the comparator and delaying a clock edge of the duty cycle according to the extracted error.

公开(公告)号：US20210067166A1

公开(公告)日：2021-03-04

申请号：US16839124

申请日：2020-04-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Xiong LIU ,  Chih-Wei YAO

IPC: H03L7/197 ,  H03L7/099 ,  H04B1/16 ,  H04L7/033

Abstract: A system, method and electronic device are provided. The system includes a shared fractional-N phase-lock loop (PLL), a ring oscillator circuit (OSC), and a multiphase injection pulse generator configured to receive an input signal having a first frequency from the shared fraction-N PLL and generate injection pulses for the OSC based on the input signal.

公开(公告)号：US20190212703A1

公开(公告)日：2019-07-11

申请号：US16040963

申请日：2018-07-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chih-Wei YAO ,  Ronghua Ni

IPC: G04F10/00 ,  H03L7/091 ,  H03L7/099 ,  H03L7/089 ,  H03M1/12

Abstract: A system and method for fast converging gain calibration for phase lock loops (PLL) are herein disclosed. According to one embodiment, a method includes receiving, with a voltage generation circuit, an input value representing a difference between a sampled voltage and a reference voltage, and adjusting, with the voltage generation circuit, the reference voltage by generating a voltage output based on the difference represented by the input value.

公开(公告)号：US20180309459A1

公开(公告)日：2018-10-25

申请号：US16017564

申请日：2018-06-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wing-Fai LOKE ,  Chih-Wei YAO

IPC: H03M1/10 ,  H03M1/18 ,  H03L7/099 ,  G04F10/00 ,  G06F17/50

CPC classification number: H03M1/1009 ,  G04F10/005 ,  G06F17/5081 ,  H03L7/0995 ,  H03L7/0996 ,  H03L7/0998 ,  H03M1/183

Abstract: An apparatus and a method are provided. The apparatus includes an analog-to-digital converter (ADC) driver; and an ADC that is electrically coupled to the ADC driver. The method includes setting, by an analog-to-digital converter (ADC) driver, a desired common-mode control value based on the held voltage; and setting, by the ADC driver, a desired gain control value based on the held voltage.