公开(公告)号：US20220157702A1

公开(公告)日：2022-05-19

申请号：US17381869

申请日：2021-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： JU-IL CHOI ,  GYUHO KANG ,  SEONG-HOON BAE ,  JIN HO AN ,  JEONGGI JIN ,  ATSUSHI FUJISAKI

IPC: H01L23/498 ,  H01L25/065 ,  H01L25/10 ,  H01L23/538 ,  H01L23/00

Abstract: A semiconductor package may include a redistribution substrate, a semiconductor chip mounted on a top surface of the redistribution substrate, and a conductive terminal provided on a bottom surface of the redistribution substrate. The redistribution substrate may include an under-bump pattern including a via portion in contact with the conductive terminal and a wire portion on the via portion and an insulating layer covering top and side surfaces of the under-bump pattern. A central portion of a bottom surface of the via portion may be provided at a level higher than an edge portion of the bottom surface of the via portion.

公开(公告)号：US20250105116A1

公开(公告)日：2025-03-27

申请号：US18974377

申请日：2024-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： JU-IL CHOI ,  GYUHO KANG ,  SEONG-HOON BAE ,  JIN HO AN ,  JEONGGI JIN ,  ATSUSHI FUJISAKI

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10

Abstract: A semiconductor package may include a redistribution substrate, a semiconductor chip mounted on a top surface of the redistribution substrate, and a conductive terminal provided on a bottom surface of the redistribution substrate. The redistribution substrate may include an under-bump pattern including a via portion in contact with the conductive terminal and a wire portion on the via portion and an insulating layer covering top and side surfaces of the under-bump pattern. A central portion of a bottom surface of the via portion may be provided at a level higher than an edge portion of the bottom surface of the via portion.

公开(公告)号：US20230103196A1

公开(公告)日：2023-03-30

申请号：US17740508

申请日：2022-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： GYUHO KANG ,  JONGHO PARK ,  SEONG-HOON BAE ,  JEONGGI JIN ,  JU-IL CHOI ,  ATSUSHI FUJISAKI

IPC: H01L23/48 ,  H01L25/10 ,  H01L23/00 ,  H01L23/498

Abstract: A semiconductor device includes a first redistribution substrate, a semiconductor chip on a top surface of the first redistribution substrate, a conductive structure on the top surface of the first redistribution substrate and laterally spaced apart from the semiconductor chip, and a molding layer on the first redistribution substrate and covering a sidewall of the semiconductor chip and a sidewall of the conductive structure. The conductive structure includes a first conductive structure having a first sidewall, and a second conductive structure on a top surface of the first conductive structure and having a second sidewall. The first conductive structure has an undercut at a lower portion of the first sidewall. The second conductive structure has a protrusion at a lower portion of the second sidewall.

公开(公告)号：US20220077043A1

公开(公告)日：2022-03-10

申请号：US17306988

申请日：2021-05-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： GYUHO KANG ,  SEONG-HOON BAE ,  JIN HO AN ,  TEAHWA JEONG ,  JU-IL CHOI ,  ATSUSHI FUJISAKI

IPC: H01L23/498 ,  H01L25/065 ,  H01L25/10 ,  H01L23/00

Abstract: A semiconductor package includes; a redistribution substrate including a redistribution pattern, a semiconductor chip mounted on a top surface of the redistribution substrate, and a connection terminal between the semiconductor chip and the redistribution substrate. The redistribution substrate further includes; a pad structure including a pad interconnection and a pad via, disposed between the redistribution pattern and the connection terminal, wherein the pad structure is electrically connected to the redistribution pattern and a top surface of the pad structure contacts the connection terminal, a shaped insulating pattern disposed on a top surface of the redistribution pattern, and a pad seed pattern disposed on the redistribution pattern and covering the shaped insulating pattern.