公开(公告)号：US20180019736A1

公开(公告)日：2018-01-18

申请号：US15649776

申请日：2017-07-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ha-Young KIM ,  DALHEE LEE ,  Hyoung-Suk OH ,  Keunho LEE ,  TAEJOONG SONG ,  SUNGWE CHO

IPC: H03K3/356 ,  H03K23/00

CPC classification number: H03K3/356104 ,  H03K3/35625 ,  H03K23/001

Abstract: A flip-flop includes an input interface, a first latch, a third inverter, and a second latch. The third inverter and the fifth inverter include first transistors of a first type formed between a first power contact and a second power contact supplied with a power supply voltage on first-type fins, and second transistors of a second type formed between a first ground contact and a second ground contact supplied with a ground voltage on second-type fins.

公开(公告)号：US20210143181A1

公开(公告)日：2021-05-13

申请号：US17153939

申请日：2021-01-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： JAE-WOO SEO ,  KI-MAN PARK ,  HA-YOUNG KIM ,  JUNGHWAN SHIN ,  KEUNHO LEE ,  SUNGWE CHO

IPC: H01L27/118 ,  H01L27/02 ,  H03K3/3562

Abstract: Disclosed is a semiconductor device including a substrate with first and second regions adjacent to each other in a first direction, and first to third gate electrodes extending from the first region toward the second region. Each of the first and second regions includes a PMOSFET region and an NMOSFET region. The first to third gate electrodes extend in the first direction and are sequentially arranged in a second direction different from the first direction. The first and third gate electrodes are supplied with a first signal. The second gate electrode is supplied with a second signal that is an inverted signal of the first signal. The first gate electrode includes a first gate of the first region and a first gate of the second region. The first gates are aligned and connected with each other in the first direction.

公开(公告)号：US20200161334A1

公开(公告)日：2020-05-21

申请号：US16669639

申请日：2019-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： JAE-WOO SEO ,  KI-MAN PARK ,  HA-YOUNG KIM ,  JUNGHWAN SHIN ,  KEUNHO LEE ,  SUNGWE CHO

IPC: H01L27/118 ,  H01L27/02 ,  H03K3/3562

Abstract: Disclosed is a semiconductor device including a substrate with first and second regions adjacent to each other in a first direction, and first to third gate electrodes extending from the first region toward the second region. Each of the first and second regions includes a PMOSFET region and an NMOSFET region. The first to third gate electrodes extend in the first direction and are sequentially arranged in a second direction different from the first direction. The first and third gate electrodes are supplied with a first signal. The second gate electrode is supplied with a second signal that is an inverted signal of the first signal. The first gate electrode includes a first gate of the first region and a first gate of the second region. The first gates are aligned and connected with each other in the first direction.

公开(公告)号：US20180173836A1

公开(公告)日：2018-06-21

申请号：US15896415

申请日：2018-02-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： TAEJOONG SONG ,  SANGHOON BAEK ,  SUNGWE CHO ,  JUNG-HO DO ,  GIYOUNG YANG ,  JINYOUNG LIM

IPC: G06F17/50 ,  H01L27/118 ,  H01L27/02

CPC classification number: G06F17/5077 ,  H01L27/0207 ,  H01L27/11807

Abstract: A method of designing a semiconductor device includes preparing a standard cell layout including a layout out a preliminary pin pattern in at least one interconnection layout, performing a routing step to connect the preliminary pin pattern to a high-level interconnection layout, and generating a pin pattern in the interconnection layout, based on hitting information obtained at the completion of the routing step. The pin pattern is smaller than the preliminary pin pattern.