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    SEMICONDUCTOR DEVICE
    1.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210126014A1

    公开(公告)日：2021-04-29

    申请号：US16989160

    申请日：2020-08-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： JINTAE KIM ,  HA-YOUNG KIM ,  SINWOO KIM ,  MOO-GYU BAE ,  JAEHA LEE

    IPC: H01L27/11597 ,  H01L27/108

    Abstract: Disclosed is a semiconductor device comprising a logic cell that is on a substrate and includes first and second active regions spaced apart from each other in a first direction, first and second active patterns that are respectively on the first and second active regions and extend in a second direction intersecting the first direction, gate electrodes extending in the first direction and running across the first and second active patterns, first connection lines that are in a first interlayer dielectric layer on the gate electrodes and extend parallel to each other in the second direction, and second connection lines that are in a second interlayer dielectric layer on the first interlayer dielectric layer and extend parallel to each other in the first direction.

    SEMICONDUCTOR DEVICE
    2.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210143181A1

    公开(公告)日：2021-05-13

    申请号：US17153939

    申请日：2021-01-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： JAE-WOO SEO ,  KI-MAN PARK ,  HA-YOUNG KIM ,  JUNGHWAN SHIN ,  KEUNHO LEE ,  SUNGWE CHO

    IPC: H01L27/118 ,  H01L27/02 ,  H03K3/3562

    Abstract: Disclosed is a semiconductor device including a substrate with first and second regions adjacent to each other in a first direction, and first to third gate electrodes extending from the first region toward the second region. Each of the first and second regions includes a PMOSFET region and an NMOSFET region. The first to third gate electrodes extend in the first direction and are sequentially arranged in a second direction different from the first direction. The first and third gate electrodes are supplied with a first signal. The second gate electrode is supplied with a second signal that is an inverted signal of the first signal. The first gate electrode includes a first gate of the first region and a first gate of the second region. The first gates are aligned and connected with each other in the first direction.

    INTEGRATED CIRCUIT AND METHOD OF DESIGNING LAYOUT OF INTEGRATED CIRCUIT
    3.
    发明申请
    INTEGRATED CIRCUIT AND METHOD OF DESIGNING LAYOUT OF INTEGRATED CIRCUIT 审中-公开

    公开(公告)号：US20180189438A1

    公开(公告)日：2018-07-05

    申请号：US15908291

    申请日：2018-02-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： JAE-WOO SEO ,  HA-YOUNG KIM ,  HYUN-JEONG ROH

    IPC: G06F17/50

    Abstract: A method of designing a layout of an integrated circuit (IC) includes placing a first cell in the layout, placing a second cell in the layout adjacent to the first cell at a first boundary between the first and second cells, and generating a plurality of commands executable by a processor to form a semiconductor device based on the layout. The first cell includes a first pattern and a second pattern. The first and second patterns are adjacent to the first boundary, the first and second patterns have different colors, and a first boundary space between the first pattern and the first boundary is different from a second boundary space between the second pattern and the first boundary.

    INTEGRATED CIRCUIT AND METHOD OF DESIGNING LAYOUT THEREOF
    4.
    发明申请
    INTEGRATED CIRCUIT AND METHOD OF DESIGNING LAYOUT THEREOF 有权
    集成电路及其布局设计方法

    公开(公告)号：US20160125117A1

    公开(公告)日：2016-05-05

    申请号：US14926128

    申请日：2015-10-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： JIN-TAE KIM ,  HA-YOUNG KIM ,  JAE-WOO SEO

    IPC: G06F17/50

    CPC classification number: G06F17/5072 ,  G06F17/5081

    Abstract: A method of designing a layout of an integrated circuit (IC), which is implemented by a computer system or a processor, includes receiving input layout data, and performing a design rule check with regard to a plurality of patterns. The method includes, merging, from among a first pattern and a second pattern against the design rule, the first pattern with a third pattern connected to a same net as the first pattern, and generating output layout data.

    Abstract translation: 设计由计算机系统或处理器实现的集成电路（IC）的布局的方法包括接收输入布局数据，以及针对多个图案执行设计规则检查。 该方法包括：从第一图案和第二图案中按照设计规则合并具有连接到与第一图案相同的网的第三图案的第一图案，以及生成输出布局数据。

    SEMICONDUCTOR DEVICE
    5.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210075406A1

    公开(公告)日：2021-03-11

    申请号：US16726379

    申请日：2019-12-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： JINTAE KIM ,  BYOUNGGON KANG ,  CHANGBEOM KIM ,  HA-YOUNG KIM ,  YONGEUN CHO

    IPC: H03K3/037 ,  H01L27/02 ,  H01L23/528 ,  H01L23/522 ,  H01L27/092 ,  H01L29/423 ,  H01L29/06

    Abstract: A semiconductor device includes a flip flop cell. The flip flop cell is formed on a semiconductor substrate, includes a flip flop circuit, and comprises a scan mux circuit, a master latch circuit, a slave latch circuit, a clock driver circuit, and an output circuit. Each of the scan mux circuit, the master latch circuit, the slave latch circuit, the clock driver circuit, and the output circuit includes a plurality of active devices which together output a resulting signal for that circuit based on inputs, is a sub-circuit of the flip flop circuit, and occupies a continuously-bounded area of the flip flop circuit from a plan view. At least a first sub-circuit and a second sub-circuit of the sub-circuits overlap from the plan view in a first overlap region, the first overlap region including part of a first continuously-bounded area for the first sub-circuit and part of a second continuously-bounded area for the second sub-circuit.

    SEMICONDUCTOR DEVICE
    6.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20200161334A1

    公开(公告)日：2020-05-21

    申请号：US16669639

    申请日：2019-10-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： JAE-WOO SEO ,  KI-MAN PARK ,  HA-YOUNG KIM ,  JUNGHWAN SHIN ,  KEUNHO LEE ,  SUNGWE CHO

    IPC: H01L27/118 ,  H01L27/02 ,  H03K3/3562

    Abstract: Disclosed is a semiconductor device including a substrate with first and second regions adjacent to each other in a first direction, and first to third gate electrodes extending from the first region toward the second region. Each of the first and second regions includes a PMOSFET region and an NMOSFET region. The first to third gate electrodes extend in the first direction and are sequentially arranged in a second direction different from the first direction. The first and third gate electrodes are supplied with a first signal. The second gate electrode is supplied with a second signal that is an inverted signal of the first signal. The first gate electrode includes a first gate of the first region and a first gate of the second region. The first gates are aligned and connected with each other in the first direction.

    SCAN FLIP-FLOP AND SCAN TEST CIRCUIT INCLUDING THE SAME
    7.
    发明申请
    SCAN FLIP-FLOP AND SCAN TEST CIRCUIT INCLUDING THE SAME 审中-公开

    公开(公告)号：US20190383875A1

    公开(公告)日：2019-12-19

    申请号：US16552109

    申请日：2019-08-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： HA-YOUNG KIM ,  SUNG-WEE CHO ,  DAL-HEE LEE ,  JAE-HA LEE

    IPC: G01R31/3185 ,  H03K3/3562

    Abstract: A scan flip-flop includes an input unit and a flip-flop. The input unit is configured to select one signal from among a data input signal and a scan input signal to supply the selected one signal as an internal signal according to an operation mode. The flip-flop is configured to latch the internal signal according to a clock signal. The flip-flop includes a cross coupled structure that includes first and second tri-state inverters which share a first output node and face each other.

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